blob: 853933715ee411500904752fd5fce53132c58565 [file] [log] [blame]
Tony Xief6118cc2016-01-15 17:17:32 +08001/*
2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
3 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Tony Xief6118cc2016-01-15 17:17:32 +08005 */
6
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +00007#ifndef SOC_H
8#define SOC_H
Tony Xief6118cc2016-01-15 17:17:32 +08009
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010#include <lib/utils.h>
Masahiro Yamada73dfd2e2016-12-05 14:28:59 +090011
Tony Xief6118cc2016-01-15 17:17:32 +080012#define GLB_SRST_FST_CFG_VAL 0xfdb9
13#define GLB_SRST_SND_CFG_VAL 0xeca8
14
Tony Xie42e113e2016-07-16 11:16:51 +080015#define PMUCRU_PPLL_CON(n) ((n) * 4)
16#define CRU_PLL_CON(pll_id, n) ((pll_id) * 0x20 + (n) * 4)
Tony Xief6118cc2016-01-15 17:17:32 +080017#define PLL_MODE_MSK 0x03
18#define PLL_MODE_SHIFT 0x08
19#define PLL_BYPASS_MSK 0x01
20#define PLL_BYPASS_SHIFT 0x01
21#define PLL_PWRDN_MSK 0x01
22#define PLL_PWRDN_SHIFT 0x0
23#define PLL_BYPASS BIT(1)
24#define PLL_PWRDN BIT(0)
25
26#define NO_PLL_BYPASS (0x00)
27#define NO_PLL_PWRDN (0x00)
28
Caesar Wang9740bba2016-08-25 08:37:42 +080029#define FBDIV(n) ((0xfff << 16) | n)
30#define POSTDIV2(n) ((0x7 << (12 + 16)) | (n << 12))
31#define POSTDIV1(n) ((0x7 << (8 + 16)) | (n << 8))
32#define REFDIV(n) ((0x3F << 16) | n)
33#define PLL_LOCK(n) ((n >> 31) & 0x1)
34
Tony Xie42e113e2016-07-16 11:16:51 +080035#define PLL_SLOW_MODE BITS_WITH_WMASK(SLOW_MODE,\
Caesar Wang59e41b52016-04-10 14:11:07 +080036 PLL_MODE_MSK, PLL_MODE_SHIFT)
Tony Xie42e113e2016-07-16 11:16:51 +080037
38#define PLL_NOMAL_MODE BITS_WITH_WMASK(NORMAL_MODE,\
Caesar Wang59e41b52016-04-10 14:11:07 +080039 PLL_MODE_MSK, PLL_MODE_SHIFT)
Tony Xief6118cc2016-01-15 17:17:32 +080040
Tony Xie42e113e2016-07-16 11:16:51 +080041#define PLL_BYPASS_MODE BIT_WITH_WMSK(PLL_BYPASS_SHIFT)
42#define PLL_NO_BYPASS_MODE WMSK_BIT(PLL_BYPASS_SHIFT)
43
Tony Xief6118cc2016-01-15 17:17:32 +080044#define PLL_CON_COUNT 0x06
Caesar Wanga8837022016-10-20 14:14:45 -070045#define CRU_CLKSEL_COUNT 108
Caesar Wang47e157c2016-09-27 18:19:30 -070046#define CRU_CLKSEL_CON(n) (0x100 + (n) * 4)
Tony Xief6118cc2016-01-15 17:17:32 +080047
48#define PMUCRU_CLKSEL_CONUT 0x06
49#define PMUCRU_CLKSEL_OFFSET 0x080
50#define REG_SIZE 0x04
51#define REG_SOC_WMSK 0xffff0000
Caesar Wang038f6aa2016-05-25 19:21:43 +080052#define CLK_GATE_MASK 0x01
53
Tony Xie42e113e2016-07-16 11:16:51 +080054#define PMUCRU_GATE_COUNT 0x03
55#define CRU_GATE_COUNT 0x23
56#define PMUCRU_GATE_CON(n) (0x100 + (n) * 4)
57#define CRU_GATE_CON(n) (0x300 + (n) * 4)
58
Lin Huang127527f2017-05-22 10:29:59 +080059#define PMUCRU_RSTNHOLD_CON0 0x120
60enum {
61 PRESETN_NOC_PMU_HOLD = 1,
62 PRESETN_INTMEM_PMU_HOLD,
63 HRESETN_CM0S_PMU_HOLD,
64 HRESETN_CM0S_NOC_PMU_HOLD,
65 DRESETN_CM0S_PMU_HOLD,
66 POESETN_CM0S_PMU_HOLD,
67 PRESETN_SPI3_HOLD,
68 RESETN_SPI3_HOLD,
69 PRESETN_TIMER_PMU_0_1_HOLD,
70 RESETN_TIMER_PMU_0_HOLD,
71 RESETN_TIMER_PMU_1_HOLD,
72 PRESETN_UART_M0_PMU_HOLD,
73 RESETN_UART_M0_PMU_HOLD,
74 PRESETN_WDT_PMU_HOLD
75};
76
77#define PMUCRU_RSTNHOLD_CON1 0x124
78enum {
79 PRESETN_I2C0_HOLD,
80 PRESETN_I2C4_HOLD,
81 PRESETN_I2C8_HOLD,
82 PRESETN_MAILBOX_PMU_HOLD,
83 PRESETN_RKPWM_PMU_HOLD,
84 PRESETN_PMUGRF_HOLD,
85 PRESETN_SGRF_HOLD,
86 PRESETN_GPIO0_HOLD,
87 PRESETN_GPIO1_HOLD,
88 PRESETN_CRU_PMU_HOLD,
89 PRESETN_INTR_ARB_HOLD,
90 PRESETN_PVTM_PMU_HOLD,
91 RESETN_I2C0_HOLD,
92 RESETN_I2C4_HOLD,
93 RESETN_I2C8_HOLD
94};
95
Tony Xief6118cc2016-01-15 17:17:32 +080096enum plls_id {
97 ALPLL_ID = 0,
98 ABPLL_ID,
99 DPLL_ID,
100 CPLL_ID,
101 GPLL_ID,
102 NPLL_ID,
103 VPLL_ID,
104 PPLL_ID,
105 END_PLL_ID,
106};
107
Tony Xie42e113e2016-07-16 11:16:51 +0800108#define CLST_L_CPUS_MSK (0xf)
109#define CLST_B_CPUS_MSK (0x3)
110
Tony Xief6118cc2016-01-15 17:17:32 +0800111enum pll_work_mode {
112 SLOW_MODE = 0x00,
113 NORMAL_MODE = 0x01,
114 DEEP_SLOW_MODE = 0x02,
115};
116
117enum glb_sft_reset {
118 PMU_RST_BY_FIRST_SFT,
119 PMU_RST_BY_SECOND_SFT = BIT(2),
120 PMU_RST_NOT_BY_SFT = BIT(3),
121};
122
Xing Zheng93280b72016-10-26 21:25:26 +0800123struct pll_div {
124 uint32_t mhz;
125 uint32_t refdiv;
126 uint32_t fbdiv;
127 uint32_t postdiv1;
128 uint32_t postdiv2;
129 uint32_t frac;
130 uint32_t freq;
131};
132
Tony Xief6118cc2016-01-15 17:17:32 +0800133struct deepsleep_data_s {
134 uint32_t plls_con[END_PLL_ID][PLL_CON_COUNT];
Tony Xie42e113e2016-07-16 11:16:51 +0800135 uint32_t cru_gate_con[CRU_GATE_COUNT];
136 uint32_t pmucru_gate_con[PMUCRU_GATE_COUNT];
Derek Basehoref900a062018-04-23 14:49:22 -0700137};
138
139struct pmu_sleep_data {
Lin Huang127527f2017-05-22 10:29:59 +0800140 uint32_t pmucru_rstnhold_con0;
141 uint32_t pmucru_rstnhold_con1;
Tony Xief6118cc2016-01-15 17:17:32 +0800142};
143
Caesar Wang9740bba2016-08-25 08:37:42 +0800144/**************************************************
145 * pmugrf reg, offset
146 **************************************************/
147#define PMUGRF_OSREG(n) (0x300 + (n) * 4)
148
149/**************************************************
150 * DCF reg, offset
151 **************************************************/
152#define DCF_DCF_CTRL 0x0
153#define DCF_DCF_ADDR 0x8
154#define DCF_DCF_ISR 0xc
155#define DCF_DCF_TOSET 0x14
156#define DCF_DCF_TOCMD 0x18
157#define DCF_DCF_CMD_CFG 0x1c
158
159/* DCF_DCF_ISR */
160#define DCF_TIMEOUT (1 << 2)
161#define DCF_ERR (1 << 1)
162#define DCF_DONE (1 << 0)
163
164/* DCF_DCF_CTRL */
165#define DCF_VOP_HW_EN (1 << 2)
166#define DCF_STOP (1 << 1)
167#define DCF_START (1 << 0)
168
Caesar Wang59e41b52016-04-10 14:11:07 +0800169#define CYCL_24M_CNT_US(us) (24 * us)
170#define CYCL_24M_CNT_MS(ms) (ms * CYCL_24M_CNT_US(1000))
Tony Xie42e113e2016-07-16 11:16:51 +0800171#define CYCL_32K_CNT_MS(ms) (ms * 32)
Caesar Wang59e41b52016-04-10 14:11:07 +0800172
Tony Xief6118cc2016-01-15 17:17:32 +0800173/**************************************************
Tony Xief6118cc2016-01-15 17:17:32 +0800174 * cru reg, offset
175 **************************************************/
176#define CRU_SOFTRST_CON(n) (0x400 + (n) * 4)
177
178#define CRU_DMAC0_RST BIT_WITH_WMSK(3)
179 /* reset release*/
180#define CRU_DMAC0_RST_RLS WMSK_BIT(3)
181
182#define CRU_DMAC1_RST BIT_WITH_WMSK(4)
183 /* reset release*/
184#define CRU_DMAC1_RST_RLS WMSK_BIT(4)
185
186#define CRU_GLB_RST_CON 0x0510
187#define CRU_GLB_SRST_FST 0x0500
188#define CRU_GLB_SRST_SND 0x0504
189
Caesar Wang038f6aa2016-05-25 19:21:43 +0800190#define CRU_CLKGATE_CON(n) (0x300 + n * 4)
191#define PCLK_GPIO2_GATE_SHIFT 3
192#define PCLK_GPIO3_GATE_SHIFT 4
193#define PCLK_GPIO4_GATE_SHIFT 5
194
Tony Xief6118cc2016-01-15 17:17:32 +0800195/**************************************************
196 * pmu cru reg, offset
197 **************************************************/
198#define CRU_PMU_RSTHOLD_CON(n) (0x120 + n * 4)
199/* reset hold*/
200#define CRU_PMU_SGRF_RST_HOLD BIT_WITH_WMSK(6)
201/* reset hold release*/
202#define CRU_PMU_SGRF_RST_RLS WMSK_BIT(6)
Caesar Wang59e41b52016-04-10 14:11:07 +0800203
204#define CRU_PMU_WDTRST_MSK (0x1 << 4)
205#define CRU_PMU_WDTRST_EN 0x0
206
207#define CRU_PMU_FIRST_SFTRST_MSK (0x3 << 2)
208#define CRU_PMU_FIRST_SFTRST_EN 0x0
209
Caesar Wang038f6aa2016-05-25 19:21:43 +0800210#define CRU_PMU_CLKGATE_CON(n) (0x100 + n * 4)
211#define PCLK_GPIO0_GATE_SHIFT 3
212#define PCLK_GPIO1_GATE_SHIFT 4
213
Tony Xief6118cc2016-01-15 17:17:32 +0800214#define CPU_BOOT_ADDR_WMASK 0xffff0000
215#define CPU_BOOT_ADDR_ALIGN 16
216
Caesar Wanged6b9a52016-08-11 02:11:45 +0800217#define GRF_IOMUX_2BIT_MASK 0x3
218#define GRF_IOMUX_GPIO 0x0
219
220#define GRF_GPIO4C2_IOMUX_SHIFT 4
221#define GRF_GPIO4C2_IOMUX_PWM 0x1
222#define GRF_GPIO4C6_IOMUX_SHIFT 12
223#define GRF_GPIO4C6_IOMUX_PWM 0x1
224
225#define PWM_CNT(n) (0x0000 + 0x10 * (n))
226#define PWM_PERIOD_HPR(n) (0x0004 + 0x10 * (n))
227#define PWM_DUTY_LPR(n) (0x0008 + 0x10 * (n))
228#define PWM_CTRL(n) (0x000c + 0x10 * (n))
229
230#define PWM_DISABLE (0 << 0)
231#define PWM_ENABLE (1 << 0)
232
Caesar Wang9740bba2016-08-25 08:37:42 +0800233/* grf reg offset */
Lin Huang2c60b5f2017-05-18 18:04:25 +0800234#define GRF_USBPHY0_CTRL0 0x4480
235#define GRF_USBPHY0_CTRL2 0x4488
236#define GRF_USBPHY0_CTRL3 0x448c
237#define GRF_USBPHY0_CTRL12 0x44b0
238#define GRF_USBPHY0_CTRL13 0x44b4
239#define GRF_USBPHY0_CTRL15 0x44bc
240#define GRF_USBPHY0_CTRL16 0x44c0
241
242#define GRF_USBPHY1_CTRL0 0x4500
243#define GRF_USBPHY1_CTRL2 0x4508
244#define GRF_USBPHY1_CTRL3 0x450c
245#define GRF_USBPHY1_CTRL12 0x4530
246#define GRF_USBPHY1_CTRL13 0x4534
247#define GRF_USBPHY1_CTRL15 0x453c
248#define GRF_USBPHY1_CTRL16 0x4540
249
250#define GRF_GPIO2A_IOMUX 0xe000
251#define GRF_GPIO2D_HE 0xe18c
Caesar Wang9740bba2016-08-25 08:37:42 +0800252#define GRF_DDRC0_CON0 0xe380
253#define GRF_DDRC0_CON1 0xe384
254#define GRF_DDRC1_CON0 0xe388
255#define GRF_DDRC1_CON1 0xe38c
Xing Zheng93280b72016-10-26 21:25:26 +0800256#define GRF_SOC_CON_BASE 0xe200
257#define GRF_SOC_CON(n) (GRF_SOC_CON_BASE + (n) * 4)
Lin Huang2c60b5f2017-05-18 18:04:25 +0800258#define GRF_IO_VSEL 0xe640
Caesar Wang9740bba2016-08-25 08:37:42 +0800259
Lin Huang2c60b5f2017-05-18 18:04:25 +0800260#define CRU_CLKSEL_CON0 0x0100
Lin Huang1f8fdeb2017-05-17 16:14:37 +0800261#define CRU_CLKSEL_CON6 0x0118
Lin Huang2c60b5f2017-05-18 18:04:25 +0800262#define CRU_SDIO0_CON1 0x058c
Caesar Wangbb228622016-10-12 01:47:51 +0800263#define PMUCRU_CLKSEL_CON0 0x0080
264#define PMUCRU_CLKGATE_CON2 0x0108
265#define PMUCRU_SOFTRST_CON0 0x0110
266#define PMUCRU_GATEDIS_CON0 0x0130
Caesar Wangbb228622016-10-12 01:47:51 +0800267#define PMUCRU_SOFTRST_CON(n) (PMUCRU_SOFTRST_CON0 + (n) * 4)
268
Xing Zheng22a98712017-02-24 14:56:41 +0800269/* export related and operating SoC APIs */
Tony Xief6118cc2016-01-15 17:17:32 +0800270void __dead2 soc_global_soft_reset(void);
Caesar Wanged6b9a52016-08-11 02:11:45 +0800271void disable_dvfs_plls(void);
272void disable_nodvfs_plls(void);
Caesar Wanged6b9a52016-08-11 02:11:45 +0800273void enable_dvfs_plls(void);
274void enable_nodvfs_plls(void);
Caesar Wang5339d182016-10-27 01:13:34 +0800275void prepare_abpll_for_ddrctrl(void);
276void restore_abpll(void);
Tony Xie42e113e2016-07-16 11:16:51 +0800277void clk_gate_con_save(void);
278void clk_gate_con_disable(void);
279void clk_gate_con_restore(void);
Lin Huang127527f2017-05-22 10:29:59 +0800280void set_pmu_rsthold(void);
Derek Basehoref900a062018-04-23 14:49:22 -0700281void pmu_sgrf_rst_hld(void);
282__pmusramfunc void pmu_sgrf_rst_hld_release(void);
283__pmusramfunc void restore_pmu_rsthold(void);
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000284#endif /* SOC_H */