rockchip: rk3399: Clean up and seprate secure parts from SoC codes
The goal is that make clear the secure and SoC codes. Now cleaning them
will help secure code extensions for RK3399 in the future.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
diff --git a/plat/rockchip/rk3399/drivers/soc/soc.h b/plat/rockchip/rk3399/drivers/soc/soc.h
index 03da025..da16adb 100644
--- a/plat/rockchip/rk3399/drivers/soc/soc.h
+++ b/plat/rockchip/rk3399/drivers/soc/soc.h
@@ -75,7 +75,6 @@
#define REG_SOC_WMSK 0xffff0000
#define CLK_GATE_MASK 0x01
-#define SGRF_SOC_COUNT 0x17
#define PMUCRU_GATE_COUNT 0x03
#define CRU_GATE_COUNT 0x23
#define PMUCRU_GATE_CON(n) (0x100 + (n) * 4)
@@ -120,11 +119,8 @@
struct deepsleep_data_s {
uint32_t plls_con[END_PLL_ID][PLL_CON_COUNT];
- uint32_t pmucru_clksel_con[PMUCRU_CLKSEL_CONUT];
- uint32_t cru_clksel_con[CRU_CLKSEL_COUNT];
uint32_t cru_gate_con[CRU_GATE_COUNT];
uint32_t pmucru_gate_con[PMUCRU_GATE_COUNT];
- uint32_t sgrf_con[SGRF_SOC_COUNT];
};
/**************************************************
@@ -157,50 +153,6 @@
#define CYCL_32K_CNT_MS(ms) (ms * 32)
/**************************************************
- * secure timer
- **************************************************/
-
-/* chanal0~5 */
-#define STIMER0_CHN_BASE(n) (STIME_BASE + 0x20 * (n))
-/* chanal6~11 */
-#define STIMER1_CHN_BASE(n) (STIME_BASE + 0x8000 + 0x20 * (n))
-
- /* low 32 bits */
-#define TIMER_END_COUNT0 0x00
- /* high 32 bits */
-#define TIMER_END_COUNT1 0x04
-
-#define TIMER_CURRENT_VALUE0 0x08
-#define TIMER_CURRENT_VALUE1 0x0C
-
- /* low 32 bits */
-#define TIMER_INIT_COUNT0 0x10
- /* high 32 bits */
-#define TIMER_INIT_COUNT1 0x14
-
-#define TIMER_INTSTATUS 0x18
-#define TIMER_CONTROL_REG 0x1c
-
-#define TIMER_EN 0x1
-
-#define TIMER_FMODE (0x0 << 1)
-#define TIMER_RMODE (0x1 << 1)
-
-/**************************************************
- * secure WDT
- **************************************************/
-#define WDT_CM0_EN 0x0
-#define WDT_CM0_DIS 0x1
-#define WDT_CA53_EN 0x0
-#define WDT_CA53_DIS 0x1
-
-#define PCLK_WDT_CA53_GATE_SHIFT 8
-#define PCLK_WDT_CM0_GATE_SHIFT 10
-
-#define WDT_CA53_1BIT_MASK 0x1
-#define WDT_CM0_1BIT_MASK 0x1
-
-/**************************************************
* cru reg, offset
**************************************************/
#define CRU_SOFTRST_CON(n) (0x400 + (n) * 4)
@@ -241,67 +193,6 @@
#define PCLK_GPIO0_GATE_SHIFT 3
#define PCLK_GPIO1_GATE_SHIFT 4
-/**************************************************
- * sgrf reg, offset
- **************************************************/
-#define SGRF_SOC_CON0_1(n) (0xc000 + (n) * 4)
-#define SGRF_SOC_CON3_7(n) (0xe00c + ((n) - 3) * 4)
-#define SGRF_SOC_CON8_15(n) (0x8020 + ((n) - 8) * 4)
-#define SGRF_PMU_SLV_CON0_1(n) (0xc240 + ((n) - 0) * 4)
-#define SGRF_SLV_SECURE_CON0_4(n) (0xe3c0 + ((n) - 0) * 4)
-#define SGRF_DDRRGN_CON0_16(n) ((n) * 4)
-#define SGRF_DDRRGN_CON20_34(n) (0x50 + ((n) - 20) * 4)
-
-/* security config for master */
-#define SGRF_SOC_CON_WMSK 0xffff0000
-/* All of master in ns */
-#define SGRF_SOC_ALLMST_NS 0xffff
-
-/* security config for slave */
-#define SGRF_SLV_S_WMSK 0xffff0000
-#define SGRF_SLV_S_ALL_NS 0x0
-
-/* security config pmu slave ip */
-/* All of slaves is ns */
-#define SGRF_PMU_SLV_S_NS BIT_WITH_WMSK(0)
-/* slaves secure attr is configed */
-#define SGRF_PMU_SLV_S_CFGED WMSK_BIT(0)
-#define SGRF_PMU_SLV_CRYPTO1_NS WMSK_BIT(1)
-
-#define SGRF_PMUSRAM_S BIT(8)
-
-#define SGRF_PMU_SLV_CON1_CFG (SGRF_SLV_S_WMSK | \
- SGRF_PMUSRAM_S)
-/* ddr region */
-#define SGRF_DDR_RGN_0_16_WMSK 0x0fff /* DDR RGN 0~16 size mask */
-
-#define SGRF_DDR_RGN_DPLL_CLK BIT_WITH_WMSK(15) /* DDR PLL output clock */
-#define SGRF_DDR_RGN_RTC_CLK BIT_WITH_WMSK(14) /* 32K clock for DDR PLL */
-#define SGRF_DDR_RGN_BYPS BIT_WITH_WMSK(9) /* All of ddr rgn is ns */
-/* All security of the DDR RGNs are not bypass */
-#define SGRF_DDR_RGN_NO_BYPS WMSK_BIT(9)
-
-/* The MST access the ddr rgn n with secure attribution */
-#define SGRF_L_MST_S_DDR_RGN(n) BIT_WITH_WMSK((n))
-/* bits[16:8]*/
-#define SGRF_H_MST_S_DDR_RGN(n) BIT_WITH_WMSK((n) + 8)
-
-/* dmac to periph s or ns*/
-#define SGRF_DMAC_CFG_S 0xffff0000
-
-#define DMAC1_RGN_NS 0xff000000
-#define DMAC0_RGN_NS 0x00ff0000
-
-#define DMAC0_BOOT_CFG_NS 0xfffffff8
-#define DMAC0_BOOT_PERIPH_NS 0xffff0fff
-#define DMAC0_BOOT_ADDR_NS 0xffff0000
-
-#define DMAC1_BOOT_CFG_NS 0xffff0008
-#define DMAC1_BOOT_PERIPH_L_NS 0xffff0fff
-#define DMAC1_BOOT_ADDR_NS 0xffff0000
-#define DMAC1_BOOT_PERIPH_H_NS 0xffffffff
-#define DMAC1_BOOT_IRQ_NS 0xffffffff
-
#define CPU_BOOT_ADDR_WMASK 0xffff0000
#define CPU_BOOT_ADDR_ALIGN 16
@@ -333,12 +224,6 @@
#define PMUCRU_CLKGATE_CON2 0x0108
#define PMUCRU_SOFTRST_CON0 0x0110
#define PMUCRU_GATEDIS_CON0 0x0130
-
-#define SGRF_SOC_CON6 0x0e018
-#define SGRF_PERILP_CON0 0x08100
-#define SGRF_PERILP_CON(n) (SGRF_PERILP_CON0 + (n) * 4)
-#define SGRF_PMU_CON0 0x0c100
-#define SGRF_PMU_CON(n) (SGRF_PMU_CON0 + (n) * 4)
#define PMUCRU_SOFTRST_CON(n) (PMUCRU_SOFTRST_CON0 + (n) * 4)
/*
@@ -362,10 +247,8 @@
CRU_PMU_SGRF_RST_HOLD);
}
-/* funciton*/
+/* export related and operating SoC APIs */
void __dead2 soc_global_soft_reset(void);
-void secure_watchdog_disable();
-void secure_watchdog_restore();
void disable_dvfs_plls(void);
void disable_nodvfs_plls(void);
void enable_dvfs_plls(void);
@@ -376,5 +259,5 @@
void clk_gate_con_save(void);
void clk_gate_con_disable(void);
void clk_gate_con_restore(void);
-void sgrf_init(void);
+
#endif /* __SOC_H__ */