Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 1 | /* |
Soby Mathew | 96a1c6b | 2018-01-15 14:45:33 +0000 | [diff] [blame] | 2 | * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 5 | */ |
| 6 | #ifndef __BOARD_ARM_DEF_H__ |
| 7 | #define __BOARD_ARM_DEF_H__ |
| 8 | |
| 9 | #include <v2m_def.h> |
| 10 | |
| 11 | |
| 12 | /* |
| 13 | * Required platform porting definitions common to all ARM |
| 14 | * development platforms |
| 15 | */ |
| 16 | |
| 17 | /* Size of cacheable stacks */ |
Masahiro Yamada | 441bfdd | 2016-12-25 23:36:24 +0900 | [diff] [blame] | 18 | #if defined(IMAGE_BL1) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 19 | #if TRUSTED_BOARD_BOOT |
| 20 | # define PLATFORM_STACK_SIZE 0x1000 |
| 21 | #else |
| 22 | # define PLATFORM_STACK_SIZE 0x440 |
| 23 | #endif |
Masahiro Yamada | 441bfdd | 2016-12-25 23:36:24 +0900 | [diff] [blame] | 24 | #elif defined(IMAGE_BL2) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 25 | # if TRUSTED_BOARD_BOOT |
| 26 | # define PLATFORM_STACK_SIZE 0x1000 |
| 27 | # else |
| 28 | # define PLATFORM_STACK_SIZE 0x400 |
| 29 | # endif |
Masahiro Yamada | 441bfdd | 2016-12-25 23:36:24 +0900 | [diff] [blame] | 30 | #elif defined(IMAGE_BL2U) |
Daniel Boulby | ec76950 | 2018-07-20 12:28:55 +0100 | [diff] [blame] | 31 | # define PLATFORM_STACK_SIZE 0x400 |
Masahiro Yamada | 441bfdd | 2016-12-25 23:36:24 +0900 | [diff] [blame] | 32 | #elif defined(IMAGE_BL31) |
Antonio Nino Diaz | 31c397f | 2018-05-24 09:14:58 +0100 | [diff] [blame] | 33 | #if ENABLE_SPM |
| 34 | # define PLATFORM_STACK_SIZE 0x500 |
| 35 | #elif PLAT_XLAT_TABLES_DYNAMIC |
Roberto Vargas | 550eb08 | 2018-01-05 16:00:05 +0000 | [diff] [blame] | 36 | # define PLATFORM_STACK_SIZE 0x800 |
| 37 | #else |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 38 | # define PLATFORM_STACK_SIZE 0x400 |
Roberto Vargas | 550eb08 | 2018-01-05 16:00:05 +0000 | [diff] [blame] | 39 | #endif |
Masahiro Yamada | 441bfdd | 2016-12-25 23:36:24 +0900 | [diff] [blame] | 40 | #elif defined(IMAGE_BL32) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 41 | # define PLATFORM_STACK_SIZE 0x440 |
| 42 | #endif |
| 43 | |
| 44 | /* |
Vikram Kanigiri | eade34c | 2016-01-20 15:57:35 +0000 | [diff] [blame] | 45 | * The constants below are not optimised for memory usage. Platforms that wish |
Antonio Nino Diaz | 30ce3ad | 2016-07-25 12:04:31 +0100 | [diff] [blame] | 46 | * to optimise these constants should set `ARM_BOARD_OPTIMISE_MEM` to 1 and |
Vikram Kanigiri | eade34c | 2016-01-20 15:57:35 +0000 | [diff] [blame] | 47 | * provide there own values. |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 48 | */ |
Antonio Nino Diaz | 30ce3ad | 2016-07-25 12:04:31 +0100 | [diff] [blame] | 49 | #if !ARM_BOARD_OPTIMISE_MEM |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 50 | /* |
Vikram Kanigiri | eade34c | 2016-01-20 15:57:35 +0000 | [diff] [blame] | 51 | * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the |
| 52 | * plat_arm_mmap array defined for each BL stage. |
| 53 | * |
| 54 | * Provide relatively optimised values for the runtime images (BL31 and BL32). |
| 55 | * Optimisation is less important for the other, transient boot images so a |
| 56 | * common, maximum value is used across these images. |
Antonio Nino Diaz | ac99803 | 2017-02-27 17:23:54 +0000 | [diff] [blame] | 57 | * |
| 58 | * They are also used for the dynamically mapped regions in the images that |
| 59 | * enable dynamic memory mapping. |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 60 | */ |
Antonio Nino Diaz | 7289f92 | 2017-11-09 11:34:09 +0000 | [diff] [blame] | 61 | #if defined(IMAGE_BL31) |
| 62 | # if ENABLE_SPM |
| 63 | # define PLAT_ARM_MMAP_ENTRIES 9 |
| 64 | # define MAX_XLAT_TABLES 7 |
| 65 | # define PLAT_SP_IMAGE_MMAP_REGIONS 7 |
| 66 | # define PLAT_SP_IMAGE_MAX_XLAT_TABLES 10 |
| 67 | # else |
Roberto Vargas | 550eb08 | 2018-01-05 16:00:05 +0000 | [diff] [blame] | 68 | # define PLAT_ARM_MMAP_ENTRIES 8 |
Antonio Nino Diaz | 7289f92 | 2017-11-09 11:34:09 +0000 | [diff] [blame] | 69 | # define MAX_XLAT_TABLES 5 |
| 70 | # endif |
| 71 | #elif defined(IMAGE_BL32) |
Roberto Vargas | 550eb08 | 2018-01-05 16:00:05 +0000 | [diff] [blame] | 72 | # define PLAT_ARM_MMAP_ENTRIES 8 |
David Cunado | c3bd8c2 | 2017-10-05 21:24:14 +0100 | [diff] [blame] | 73 | # define MAX_XLAT_TABLES 5 |
Roberto Vargas | e3adc37 | 2018-05-23 09:27:06 +0100 | [diff] [blame] | 74 | #elif !USE_ROMLIB |
David Cunado | c3bd8c2 | 2017-10-05 21:24:14 +0100 | [diff] [blame] | 75 | # define PLAT_ARM_MMAP_ENTRIES 11 |
David Wang | 0ba499f | 2016-03-07 11:02:57 +0800 | [diff] [blame] | 76 | # define MAX_XLAT_TABLES 5 |
Roberto Vargas | e3adc37 | 2018-05-23 09:27:06 +0100 | [diff] [blame] | 77 | #else |
| 78 | # define PLAT_ARM_MMAP_ENTRIES 12 |
| 79 | # define MAX_XLAT_TABLES 6 |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 80 | #endif |
| 81 | |
Antonio Nino Diaz | 30ce3ad | 2016-07-25 12:04:31 +0100 | [diff] [blame] | 82 | /* |
| 83 | * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size |
| 84 | * plus a little space for growth. |
| 85 | */ |
Qixiang Xu | a674feb | 2017-08-24 14:28:08 +0800 | [diff] [blame] | 86 | #define PLAT_ARM_MAX_BL1_RW_SIZE 0xB000 |
Antonio Nino Diaz | 30ce3ad | 2016-07-25 12:04:31 +0100 | [diff] [blame] | 87 | |
| 88 | /* |
Roberto Vargas | e3adc37 | 2018-05-23 09:27:06 +0100 | [diff] [blame] | 89 | * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page |
| 90 | */ |
| 91 | |
| 92 | #if USE_ROMLIB |
| 93 | #define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0x1000 |
| 94 | #define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0xe000 |
| 95 | #else |
| 96 | #define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0 |
| 97 | #define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0 |
| 98 | #endif |
| 99 | |
| 100 | /* |
Antonio Nino Diaz | 30ce3ad | 2016-07-25 12:04:31 +0100 | [diff] [blame] | 101 | * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a |
| 102 | * little space for growth. |
| 103 | */ |
| 104 | #if TRUSTED_BOARD_BOOT |
John Tsichritzis | 1d4c505 | 2018-09-03 15:06:44 +0100 | [diff] [blame] | 105 | # define PLAT_ARM_MAX_BL2_SIZE 0x1C000 |
Antonio Nino Diaz | 30ce3ad | 2016-07-25 12:04:31 +0100 | [diff] [blame] | 106 | #else |
Antonio Nino Diaz | 23ede6a | 2018-06-19 09:29:36 +0100 | [diff] [blame] | 107 | # define PLAT_ARM_MAX_BL2_SIZE 0x11000 |
Antonio Nino Diaz | 30ce3ad | 2016-07-25 12:04:31 +0100 | [diff] [blame] | 108 | #endif |
| 109 | |
| 110 | /* |
Soby Mathew | af14b46 | 2018-06-01 16:53:38 +0100 | [diff] [blame] | 111 | * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is |
| 112 | * calculated using the current BL31 PROGBITS debug size plus the sizes of |
| 113 | * BL2 and BL1-RW |
Antonio Nino Diaz | 30ce3ad | 2016-07-25 12:04:31 +0100 | [diff] [blame] | 114 | */ |
Soby Mathew | af14b46 | 2018-06-01 16:53:38 +0100 | [diff] [blame] | 115 | #define PLAT_ARM_MAX_BL31_SIZE 0x3B000 |
Antonio Nino Diaz | 30ce3ad | 2016-07-25 12:04:31 +0100 | [diff] [blame] | 116 | |
Soby Mathew | bf16923 | 2017-11-14 14:10:10 +0000 | [diff] [blame] | 117 | #ifdef AARCH32 |
| 118 | /* |
Soby Mathew | af14b46 | 2018-06-01 16:53:38 +0100 | [diff] [blame] | 119 | * Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL32_SIZE is |
| 120 | * calculated using the current SP_MIN PROGBITS debug size plus the sizes of |
| 121 | * BL2 and BL1-RW |
Soby Mathew | bf16923 | 2017-11-14 14:10:10 +0000 | [diff] [blame] | 122 | */ |
Soby Mathew | af14b46 | 2018-06-01 16:53:38 +0100 | [diff] [blame] | 123 | # define PLAT_ARM_MAX_BL32_SIZE 0x3B000 |
Soby Mathew | bf16923 | 2017-11-14 14:10:10 +0000 | [diff] [blame] | 124 | #endif |
| 125 | |
Antonio Nino Diaz | 30ce3ad | 2016-07-25 12:04:31 +0100 | [diff] [blame] | 126 | #endif /* ARM_BOARD_OPTIMISE_MEM */ |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 127 | |
| 128 | #define MAX_IO_DEVICES 3 |
| 129 | #define MAX_IO_HANDLES 4 |
| 130 | |
| 131 | #define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00040000 /* 256 KB */ |
| 132 | |
Roberto Vargas | a1c16b6 | 2017-08-03 09:16:43 +0100 | [diff] [blame] | 133 | /* Reserve the last block of flash for PSCI MEM PROTECT flag */ |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 134 | #define PLAT_ARM_FIP_BASE V2M_FLASH0_BASE |
Roberto Vargas | a1c16b6 | 2017-08-03 09:16:43 +0100 | [diff] [blame] | 135 | #define PLAT_ARM_FIP_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 136 | |
Yatharth Kochar | f11b29a | 2016-02-01 11:04:46 +0000 | [diff] [blame] | 137 | #define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE |
Roberto Vargas | a1c16b6 | 2017-08-03 09:16:43 +0100 | [diff] [blame] | 138 | #define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) |
| 139 | |
Roberto Vargas | a1c16b6 | 2017-08-03 09:16:43 +0100 | [diff] [blame] | 140 | /* |
| 141 | * Map mem_protect flash region with read and write permissions |
| 142 | */ |
| 143 | #define ARM_V2M_MAP_MEM_PROTECT MAP_REGION_FLAT(PLAT_ARM_MEM_PROT_ADDR, \ |
| 144 | V2M_FLASH_BLOCK_SIZE, \ |
| 145 | MT_DEVICE | MT_RW | MT_SECURE) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 146 | |
| 147 | #endif /* __BOARD_ARM_DEF_H__ */ |