Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 1 | /* |
Vikram Kanigiri | 0703543 | 2015-11-12 18:52:34 +0000 | [diff] [blame] | 2 | * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | #ifndef __PLAT_ARM_H__ |
| 31 | #define __PLAT_ARM_H__ |
| 32 | |
| 33 | #include <bakery_lock.h> |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 34 | #include <cassert.h> |
| 35 | #include <cpu_data.h> |
| 36 | #include <stdint.h> |
Sandrine Bailleux | 7659a26 | 2016-07-05 09:55:03 +0100 | [diff] [blame] | 37 | #include <utils.h> |
Soby Mathew | fe3b576 | 2015-10-27 10:31:35 +0000 | [diff] [blame] | 38 | #include <xlat_tables.h> |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 39 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 40 | #define ARM_CASSERT_MMAP \ |
| 41 | CASSERT((ARRAY_SIZE(plat_arm_mmap) + ARM_BL_REGIONS) \ |
| 42 | <= MAX_MMAP_REGIONS, \ |
| 43 | assert_max_mmap_regions); |
| 44 | |
| 45 | /* |
| 46 | * Utility functions common to ARM standard platforms |
| 47 | */ |
Soby Mathew | a0fedc4 | 2016-06-16 14:52:04 +0100 | [diff] [blame] | 48 | void arm_setup_page_tables(uintptr_t total_base, |
| 49 | size_t total_size, |
| 50 | uintptr_t code_start, |
| 51 | uintptr_t code_limit, |
| 52 | uintptr_t rodata_start, |
| 53 | uintptr_t rodata_limit |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 54 | #if USE_COHERENT_MEM |
Soby Mathew | a0fedc4 | 2016-06-16 14:52:04 +0100 | [diff] [blame] | 55 | , uintptr_t coh_start, |
| 56 | uintptr_t coh_limit |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 57 | #endif |
| 58 | ); |
| 59 | |
| 60 | #if IMAGE_BL31 |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 61 | /* |
| 62 | * Use this macro to instantiate lock before it is used in below |
| 63 | * arm_lock_xxx() macros |
| 64 | */ |
Vikram Kanigiri | d79214c | 2015-09-09 10:52:13 +0100 | [diff] [blame] | 65 | #define ARM_INSTANTIATE_LOCK DEFINE_BAKERY_LOCK(arm_lock); |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 66 | |
| 67 | /* |
| 68 | * These are wrapper macros to the Coherent Memory Bakery Lock API. |
| 69 | */ |
| 70 | #define arm_lock_init() bakery_lock_init(&arm_lock) |
| 71 | #define arm_lock_get() bakery_lock_get(&arm_lock) |
| 72 | #define arm_lock_release() bakery_lock_release(&arm_lock) |
| 73 | |
| 74 | #else |
| 75 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 76 | /* |
Juan Castillo | 7d19941 | 2015-12-14 09:35:25 +0000 | [diff] [blame] | 77 | * Empty macros for all other BL stages other than BL31 |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 78 | */ |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 79 | #define ARM_INSTANTIATE_LOCK |
| 80 | #define arm_lock_init() |
| 81 | #define arm_lock_get() |
| 82 | #define arm_lock_release() |
| 83 | |
| 84 | #endif /* IMAGE_BL31 */ |
| 85 | |
Soby Mathew | 7799cf7 | 2015-04-16 14:49:09 +0100 | [diff] [blame] | 86 | #if ARM_RECOM_STATE_ID_ENC |
| 87 | /* |
| 88 | * Macros used to parse state information from State-ID if it is using the |
| 89 | * recommended encoding for State-ID. |
| 90 | */ |
| 91 | #define ARM_LOCAL_PSTATE_WIDTH 4 |
| 92 | #define ARM_LOCAL_PSTATE_MASK ((1 << ARM_LOCAL_PSTATE_WIDTH) - 1) |
| 93 | |
| 94 | /* Macros to construct the composite power state */ |
| 95 | |
| 96 | /* Make composite power state parameter till power level 0 */ |
| 97 | #if PSCI_EXTENDED_STATE_ID |
| 98 | |
| 99 | #define arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ |
| 100 | (((lvl0_state) << PSTATE_ID_SHIFT) | ((type) << PSTATE_TYPE_SHIFT)) |
| 101 | #else |
| 102 | #define arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ |
| 103 | (((lvl0_state) << PSTATE_ID_SHIFT) | \ |
| 104 | ((pwr_lvl) << PSTATE_PWR_LVL_SHIFT) | \ |
| 105 | ((type) << PSTATE_TYPE_SHIFT)) |
| 106 | #endif /* __PSCI_EXTENDED_STATE_ID__ */ |
| 107 | |
| 108 | /* Make composite power state parameter till power level 1 */ |
| 109 | #define arm_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type) \ |
| 110 | (((lvl1_state) << ARM_LOCAL_PSTATE_WIDTH) | \ |
| 111 | arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type)) |
| 112 | |
Soby Mathew | a869de1 | 2015-05-08 10:18:59 +0100 | [diff] [blame] | 113 | /* Make composite power state parameter till power level 2 */ |
| 114 | #define arm_make_pwrstate_lvl2(lvl2_state, lvl1_state, lvl0_state, pwr_lvl, type) \ |
| 115 | (((lvl2_state) << (ARM_LOCAL_PSTATE_WIDTH * 2)) | \ |
| 116 | arm_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type)) |
| 117 | |
Soby Mathew | 7799cf7 | 2015-04-16 14:49:09 +0100 | [diff] [blame] | 118 | #endif /* __ARM_RECOM_STATE_ID_ENC__ */ |
| 119 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 120 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 121 | /* IO storage utility functions */ |
| 122 | void arm_io_setup(void); |
| 123 | |
| 124 | /* Security utility functions */ |
Soby Mathew | 9c708b5 | 2016-02-26 14:23:19 +0000 | [diff] [blame] | 125 | void arm_tzc400_setup(void); |
Vikram Kanigiri | 510d87b | 2016-01-29 12:32:58 +0000 | [diff] [blame] | 126 | struct tzc_dmc500_driver_data; |
| 127 | void arm_tzc_dmc500_setup(struct tzc_dmc500_driver_data *plat_driver_data); |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 128 | |
Soby Mathew | 61e8d0b | 2015-10-12 17:32:29 +0100 | [diff] [blame] | 129 | /* Systimer utility function */ |
| 130 | void arm_configure_sys_timer(void); |
| 131 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 132 | /* PM utility functions */ |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 133 | int arm_validate_power_state(unsigned int power_state, |
| 134 | psci_power_state_t *req_state); |
Soby Mathew | 0d9e852 | 2015-07-15 13:36:24 +0100 | [diff] [blame] | 135 | int arm_validate_ns_entrypoint(uintptr_t entrypoint); |
Soby Mathew | 61e8d0b | 2015-10-12 17:32:29 +0100 | [diff] [blame] | 136 | void arm_system_pwr_domain_resume(void); |
Sandrine Bailleux | 03897bb | 2015-11-26 16:31:34 +0000 | [diff] [blame] | 137 | void arm_program_trusted_mailbox(uintptr_t address); |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 138 | |
| 139 | /* Topology utility function */ |
| 140 | int arm_check_mpidr(u_register_t mpidr); |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 141 | |
| 142 | /* BL1 utility functions */ |
| 143 | void arm_bl1_early_platform_setup(void); |
| 144 | void arm_bl1_platform_setup(void); |
| 145 | void arm_bl1_plat_arch_setup(void); |
| 146 | |
| 147 | /* BL2 utility functions */ |
| 148 | void arm_bl2_early_platform_setup(meminfo_t *mem_layout); |
| 149 | void arm_bl2_platform_setup(void); |
| 150 | void arm_bl2_plat_arch_setup(void); |
| 151 | uint32_t arm_get_spsr_for_bl32_entry(void); |
| 152 | uint32_t arm_get_spsr_for_bl33_entry(void); |
| 153 | |
Yatharth Kochar | 3a11eda | 2015-10-14 15:28:11 +0100 | [diff] [blame] | 154 | /* BL2U utility functions */ |
| 155 | void arm_bl2u_early_platform_setup(struct meminfo *mem_layout, |
| 156 | void *plat_info); |
| 157 | void arm_bl2u_platform_setup(void); |
| 158 | void arm_bl2u_plat_arch_setup(void); |
| 159 | |
Juan Castillo | 7d19941 | 2015-12-14 09:35:25 +0000 | [diff] [blame] | 160 | /* BL31 utility functions */ |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 161 | void arm_bl31_early_platform_setup(bl31_params_t *from_bl2, |
| 162 | void *plat_params_from_bl2); |
| 163 | void arm_bl31_platform_setup(void); |
Soby Mathew | 2fd66be | 2015-12-09 11:38:43 +0000 | [diff] [blame] | 164 | void arm_bl31_plat_runtime_setup(void); |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 165 | void arm_bl31_plat_arch_setup(void); |
| 166 | |
| 167 | /* TSP utility functions */ |
| 168 | void arm_tsp_early_platform_setup(void); |
| 169 | |
Yatharth Kochar | 736a3bf | 2015-10-11 14:14:55 +0100 | [diff] [blame] | 170 | /* FIP TOC validity check */ |
| 171 | int arm_io_is_toc_valid(void); |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 172 | |
| 173 | /* |
| 174 | * Mandatory functions required in ARM standard platforms |
| 175 | */ |
Soby Mathew | 47e43f2 | 2016-02-01 14:04:34 +0000 | [diff] [blame] | 176 | unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr); |
Achin Gupta | 1fa7eb6 | 2015-11-03 14:18:34 +0000 | [diff] [blame] | 177 | void plat_arm_gic_driver_init(void); |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 178 | void plat_arm_gic_init(void); |
Achin Gupta | 1fa7eb6 | 2015-11-03 14:18:34 +0000 | [diff] [blame] | 179 | void plat_arm_gic_cpuif_enable(void); |
| 180 | void plat_arm_gic_cpuif_disable(void); |
| 181 | void plat_arm_gic_pcpu_init(void); |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 182 | void plat_arm_security_setup(void); |
| 183 | void plat_arm_pwrc_setup(void); |
Vikram Kanigiri | fbb1301 | 2016-02-15 11:54:14 +0000 | [diff] [blame] | 184 | void plat_arm_interconnect_init(void); |
| 185 | void plat_arm_interconnect_enter_coherency(void); |
| 186 | void plat_arm_interconnect_exit_coherency(void); |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 187 | |
| 188 | /* |
| 189 | * Optional functions required in ARM standard platforms |
| 190 | */ |
| 191 | void plat_arm_io_setup(void); |
| 192 | int plat_arm_get_alt_image_source( |
Juan Castillo | 3a66aca | 2015-04-13 17:36:19 +0100 | [diff] [blame] | 193 | unsigned int image_id, |
| 194 | uintptr_t *dev_handle, |
| 195 | uintptr_t *image_spec); |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 196 | unsigned int plat_arm_calc_core_pos(u_register_t mpidr); |
Vikram Kanigiri | 0703543 | 2015-11-12 18:52:34 +0000 | [diff] [blame] | 197 | const mmap_region_t *plat_arm_get_mmap(void); |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 198 | |
| 199 | #endif /* __PLAT_ARM_H__ */ |