Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
Soby Mathew | 73308d0 | 2018-01-09 14:36:14 +0000 | [diff] [blame] | 2 | * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 5 | */ |
| 6 | |
Sandrine Bailleux | c10bd2c | 2013-11-12 16:41:16 +0000 | [diff] [blame] | 7 | #include <arch.h> |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 8 | #include <asm_macros.S> |
Dan Handley | 2bd4ef2 | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 9 | #include <bl_common.h> |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 10 | |
| 11 | |
| 12 | .globl bl2_entrypoint |
| 13 | |
| 14 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 15 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 16 | func bl2_entrypoint |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 17 | /*--------------------------------------------- |
Soby Mathew | 73308d0 | 2018-01-09 14:36:14 +0000 | [diff] [blame] | 18 | * Save arguments x0 - x3 from BL1 for future |
| 19 | * use. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 20 | * --------------------------------------------- |
Antonio Nino Diaz | 1f21bcf | 2016-02-01 13:57:25 +0000 | [diff] [blame] | 21 | */ |
Soby Mathew | 73308d0 | 2018-01-09 14:36:14 +0000 | [diff] [blame] | 22 | mov x20, x0 |
| 23 | mov x21, x1 |
| 24 | mov x22, x2 |
| 25 | mov x23, x3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 26 | |
| 27 | /* --------------------------------------------- |
Sandrine Bailleux | c10bd2c | 2013-11-12 16:41:16 +0000 | [diff] [blame] | 28 | * Set the exception vector to something sane. |
| 29 | * --------------------------------------------- |
| 30 | */ |
| 31 | adr x0, early_exceptions |
| 32 | msr vbar_el1, x0 |
Achin Gupta | ed1744e | 2014-08-04 23:13:10 +0100 | [diff] [blame] | 33 | isb |
| 34 | |
| 35 | /* --------------------------------------------- |
| 36 | * Enable the SError interrupt now that the |
| 37 | * exception vectors have been setup. |
| 38 | * --------------------------------------------- |
| 39 | */ |
| 40 | msr daifclr, #DAIF_ABT_BIT |
Sandrine Bailleux | c10bd2c | 2013-11-12 16:41:16 +0000 | [diff] [blame] | 41 | |
| 42 | /* --------------------------------------------- |
Achin Gupta | 9f09835 | 2014-07-18 18:38:28 +0100 | [diff] [blame] | 43 | * Enable the instruction cache, stack pointer |
| 44 | * and data access alignment checks |
Sandrine Bailleux | c10bd2c | 2013-11-12 16:41:16 +0000 | [diff] [blame] | 45 | * --------------------------------------------- |
| 46 | */ |
Achin Gupta | 9f09835 | 2014-07-18 18:38:28 +0100 | [diff] [blame] | 47 | mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) |
Sandrine Bailleux | c10bd2c | 2013-11-12 16:41:16 +0000 | [diff] [blame] | 48 | mrs x0, sctlr_el1 |
Achin Gupta | 9f09835 | 2014-07-18 18:38:28 +0100 | [diff] [blame] | 49 | orr x0, x0, x1 |
Sandrine Bailleux | c10bd2c | 2013-11-12 16:41:16 +0000 | [diff] [blame] | 50 | msr sctlr_el1, x0 |
Sandrine Bailleux | c10bd2c | 2013-11-12 16:41:16 +0000 | [diff] [blame] | 51 | isb |
| 52 | |
Sandrine Bailleux | 65f546a | 2013-11-28 09:43:06 +0000 | [diff] [blame] | 53 | /* --------------------------------------------- |
Achin Gupta | e9c4a64 | 2015-09-11 16:03:13 +0100 | [diff] [blame] | 54 | * Invalidate the RW memory used by the BL2 |
| 55 | * image. This includes the data and NOBITS |
| 56 | * sections. This is done to safeguard against |
| 57 | * possible corruption of this memory by dirty |
| 58 | * cache lines in a system cache as a result of |
| 59 | * use by an earlier boot loader stage. |
| 60 | * --------------------------------------------- |
| 61 | */ |
| 62 | adr x0, __RW_START__ |
| 63 | adr x1, __RW_END__ |
| 64 | sub x1, x1, x0 |
| 65 | bl inv_dcache_range |
| 66 | |
| 67 | /* --------------------------------------------- |
Sandrine Bailleux | 65f546a | 2013-11-28 09:43:06 +0000 | [diff] [blame] | 68 | * Zero out NOBITS sections. There are 2 of them: |
| 69 | * - the .bss section; |
| 70 | * - the coherent memory section. |
| 71 | * --------------------------------------------- |
| 72 | */ |
| 73 | ldr x0, =__BSS_START__ |
| 74 | ldr x1, =__BSS_SIZE__ |
Douglas Raillard | 21362a9 | 2016-12-02 13:51:54 +0000 | [diff] [blame] | 75 | bl zeromem |
Sandrine Bailleux | 65f546a | 2013-11-28 09:43:06 +0000 | [diff] [blame] | 76 | |
Soby Mathew | 2ae2043 | 2015-01-08 18:02:44 +0000 | [diff] [blame] | 77 | #if USE_COHERENT_MEM |
Sandrine Bailleux | 65f546a | 2013-11-28 09:43:06 +0000 | [diff] [blame] | 78 | ldr x0, =__COHERENT_RAM_START__ |
| 79 | ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__ |
Douglas Raillard | 21362a9 | 2016-12-02 13:51:54 +0000 | [diff] [blame] | 80 | bl zeromem |
Soby Mathew | 2ae2043 | 2015-01-08 18:02:44 +0000 | [diff] [blame] | 81 | #endif |
Sandrine Bailleux | 65f546a | 2013-11-28 09:43:06 +0000 | [diff] [blame] | 82 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 83 | /* -------------------------------------------- |
Achin Gupta | f4a9709 | 2014-06-25 19:26:22 +0100 | [diff] [blame] | 84 | * Allocate a stack whose memory will be marked |
| 85 | * as Normal-IS-WBWA when the MMU is enabled. |
| 86 | * There is no risk of reading stale stack |
| 87 | * memory after enabling the MMU as only the |
| 88 | * primary cpu is running at the moment. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 89 | * -------------------------------------------- |
| 90 | */ |
Soby Mathew | 3700a92 | 2015-07-13 11:21:11 +0100 | [diff] [blame] | 91 | bl plat_set_my_stack |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 92 | |
| 93 | /* --------------------------------------------- |
Douglas Raillard | 306593d | 2017-02-24 18:14:15 +0000 | [diff] [blame] | 94 | * Initialize the stack protector canary before |
| 95 | * any C code is called. |
| 96 | * --------------------------------------------- |
| 97 | */ |
| 98 | #if STACK_PROTECTOR_ENABLED |
| 99 | bl update_stack_protector_canary |
| 100 | #endif |
| 101 | |
| 102 | /* --------------------------------------------- |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 103 | * Perform early platform setup & platform |
| 104 | * specific early arch. setup e.g. mmu setup |
| 105 | * --------------------------------------------- |
| 106 | */ |
Yatharth Kochar | 57d334c | 2015-10-29 12:47:02 +0000 | [diff] [blame] | 107 | mov x0, x20 |
Soby Mathew | 73308d0 | 2018-01-09 14:36:14 +0000 | [diff] [blame] | 108 | mov x1, x21 |
| 109 | mov x2, x22 |
| 110 | mov x3, x23 |
| 111 | bl bl2_early_platform_setup2 |
| 112 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 113 | bl bl2_plat_arch_setup |
| 114 | |
| 115 | /* --------------------------------------------- |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 116 | * Jump to main function. |
| 117 | * --------------------------------------------- |
| 118 | */ |
| 119 | bl bl2_main |
Antonio Nino Diaz | 1f21bcf | 2016-02-01 13:57:25 +0000 | [diff] [blame] | 120 | |
| 121 | /* --------------------------------------------- |
| 122 | * Should never reach this point. |
| 123 | * --------------------------------------------- |
| 124 | */ |
Jeenu Viswambharan | 68aef10 | 2016-11-30 15:21:11 +0000 | [diff] [blame] | 125 | no_ret plat_panic_handler |
Antonio Nino Diaz | 1f21bcf | 2016-02-01 13:57:25 +0000 | [diff] [blame] | 126 | |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 127 | endfunc bl2_entrypoint |