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git01.mediatek.com / filogic / atf / b9831eda66fd8fe2d696853a290e19638ed3a5fa / . / include / plat / arm / board / common / board_css_def.h
blob: 6cca38909ac2a291ef418bcf173a737e0049c868 [file] [log] [blame]
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]1/*
David Cunado2e36de82017-01-19 10:26:16 +0000[diff] [blame]2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]3 *
dp-armfa3cf0b2017-05-03 09:38:09 +0100[diff] [blame]4 * SPDX-License-Identifier: BSD-3-Clause
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]5 */
6
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000[diff] [blame]7#ifndef BOARD_CSS_DEF_H
8#define BOARD_CSS_DEF_H
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]9
Antonio Nino Diaze0f90632018-12-14 00:18:21 +0000[diff] [blame]10#include <lib/utils_def.h>
11#include <plat/common/common_def.h>
12
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]13#include <soc_css_def.h>
14#include <v2m_def.h>
15
16/*
17 * Definitions common to all ARM CSS-based development platforms
18 */
19
20/* Platform ID address */
21#define BOARD_CSS_PLAT_ID_REG_ADDR 0x7ffe00e0
22
23/* Platform ID related accessors */
24#define BOARD_CSS_PLAT_ID_REG_ID_MASK 0x0f
25#define BOARD_CSS_PLAT_ID_REG_ID_SHIFT 0x0
26#define BOARD_CSS_PLAT_ID_REG_VERSION_MASK 0xf00
27#define BOARD_CSS_PLAT_ID_REG_VERSION_SHIFT 0x8
28#define BOARD_CSS_PLAT_TYPE_RTL 0x00
29#define BOARD_CSS_PLAT_TYPE_FPGA 0x01
30#define BOARD_CSS_PLAT_TYPE_EMULATOR 0x02
31#define BOARD_CSS_PLAT_TYPE_FVP 0x03
32
33#ifndef __ASSEMBLY__
34
Antonio Nino Diaze0f90632018-12-14 00:18:21 +0000[diff] [blame]35#include <lib/mmio.h>
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]36
37#define BOARD_CSS_GET_PLAT_TYPE(addr) \
38 ((mmio_read_32(addr) & BOARD_CSS_PLAT_ID_REG_ID_MASK) \
39 >> BOARD_CSS_PLAT_ID_REG_ID_SHIFT)
40
41#endif /* __ASSEMBLY__ */
42
43
Antonio Nino Diaz48bfb542018-10-11 13:02:34 +0100[diff] [blame]44#define MAX_IO_DEVICES 3
45#define MAX_IO_HANDLES 4
46
47/* Reserve the last block of flash for PSCI MEM PROTECT flag */
48#define PLAT_ARM_FIP_BASE V2M_FLASH0_BASE
49#define PLAT_ARM_FIP_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
50
51#define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE
52#define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
53
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]54/*
55 * Required platform porting definitions common to all ARM CSS-based
56 * development platforms
57 */
58
David Cunado2e36de82017-01-19 10:26:16 +0000[diff] [blame]59#define PLAT_ARM_DRAM2_SIZE ULL(0x180000000)
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]60
61/* UART related constants */
62#define PLAT_ARM_BOOT_UART_BASE SOC_CSS_UART0_BASE
63#define PLAT_ARM_BOOT_UART_CLK_IN_HZ SOC_CSS_UART0_CLK_IN_HZ
64
Soby Mathew2fd66be2015-12-09 11:38:43 +0000[diff] [blame]65#define PLAT_ARM_BL31_RUN_UART_BASE SOC_CSS_UART1_BASE
66#define PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ SOC_CSS_UART1_CLK_IN_HZ
67
Dimitris Papastamos52323b02017-06-07 13:45:41 +0100[diff] [blame]68#define PLAT_ARM_SP_MIN_RUN_UART_BASE SOC_CSS_UART1_BASE
69#define PLAT_ARM_SP_MIN_RUN_UART_CLK_IN_HZ SOC_CSS_UART1_CLK_IN_HZ
70
Soby Mathew2fd66be2015-12-09 11:38:43 +0000[diff] [blame]71#define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_BL31_RUN_UART_BASE
72#define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]73
74#define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART0_BASE
75#define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ
76
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000[diff] [blame]77#endif /* BOARD_CSS_DEF_H */