| Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 1 | /* |
| David Cunado | 2e36de8 | 2017-01-19 10:26:16 +0000 | [diff] [blame] | 2 | * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. |
| Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 3 | * |
| dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame^] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
| Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef __BOARD_CSS_DEF_H__ |
| 8 | #define __BOARD_CSS_DEF_H__ |
| 9 | |
| 10 | #include <common_def.h> |
| 11 | #include <soc_css_def.h> |
| Scott Branden | bf404c0 | 2017-04-10 11:45:52 -0700 | [diff] [blame] | 12 | #include <utils_def.h> |
| Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 13 | #include <v2m_def.h> |
| 14 | |
| 15 | /* |
| 16 | * Definitions common to all ARM CSS-based development platforms |
| 17 | */ |
| 18 | |
| 19 | /* Platform ID address */ |
| 20 | #define BOARD_CSS_PLAT_ID_REG_ADDR 0x7ffe00e0 |
| 21 | |
| 22 | /* Platform ID related accessors */ |
| 23 | #define BOARD_CSS_PLAT_ID_REG_ID_MASK 0x0f |
| 24 | #define BOARD_CSS_PLAT_ID_REG_ID_SHIFT 0x0 |
| 25 | #define BOARD_CSS_PLAT_ID_REG_VERSION_MASK 0xf00 |
| 26 | #define BOARD_CSS_PLAT_ID_REG_VERSION_SHIFT 0x8 |
| 27 | #define BOARD_CSS_PLAT_TYPE_RTL 0x00 |
| 28 | #define BOARD_CSS_PLAT_TYPE_FPGA 0x01 |
| 29 | #define BOARD_CSS_PLAT_TYPE_EMULATOR 0x02 |
| 30 | #define BOARD_CSS_PLAT_TYPE_FVP 0x03 |
| 31 | |
| 32 | #ifndef __ASSEMBLY__ |
| 33 | |
| 34 | #include <mmio.h> |
| 35 | |
| 36 | #define BOARD_CSS_GET_PLAT_TYPE(addr) \ |
| 37 | ((mmio_read_32(addr) & BOARD_CSS_PLAT_ID_REG_ID_MASK) \ |
| 38 | >> BOARD_CSS_PLAT_ID_REG_ID_SHIFT) |
| 39 | |
| 40 | #endif /* __ASSEMBLY__ */ |
| 41 | |
| 42 | |
| 43 | /* |
| 44 | * Required platform porting definitions common to all ARM CSS-based |
| 45 | * development platforms |
| 46 | */ |
| 47 | |
| David Cunado | 2e36de8 | 2017-01-19 10:26:16 +0000 | [diff] [blame] | 48 | #define PLAT_ARM_DRAM2_SIZE ULL(0x180000000) |
| Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 49 | |
| 50 | /* UART related constants */ |
| 51 | #define PLAT_ARM_BOOT_UART_BASE SOC_CSS_UART0_BASE |
| 52 | #define PLAT_ARM_BOOT_UART_CLK_IN_HZ SOC_CSS_UART0_CLK_IN_HZ |
| 53 | |
| Soby Mathew | 2fd66be | 2015-12-09 11:38:43 +0000 | [diff] [blame] | 54 | #define PLAT_ARM_BL31_RUN_UART_BASE SOC_CSS_UART1_BASE |
| 55 | #define PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ SOC_CSS_UART1_CLK_IN_HZ |
| 56 | |
| 57 | #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_BL31_RUN_UART_BASE |
| 58 | #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ |
| Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 59 | |
| 60 | #define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART0_BASE |
| 61 | #define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ |
| 62 | |
| 63 | |
| 64 | #endif /* __BOARD_CSS_DEF_H__ */ |
| 65 | |