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Achin Gupta92712a52015-09-03 14:18:02 +01001/*
Jeenu Viswambharanb6982c02018-03-22 08:57:52 +00002 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
Achin Gupta92712a52015-09-03 14:18:02 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta92712a52015-09-03 14:18:02 +01005 */
6
7#ifndef __GIC_COMMON_H__
8#define __GIC_COMMON_H__
9
10/*******************************************************************************
11 * GIC Distributor interface general definitions
12 ******************************************************************************/
13/* Constants to categorise interrupts */
14#define MIN_SGI_ID 0
Jeenu Viswambharan522a4652017-09-22 08:32:09 +010015#define MIN_SEC_SGI_ID 8
Achin Gupta92712a52015-09-03 14:18:02 +010016#define MIN_PPI_ID 16
17#define MIN_SPI_ID 32
Soby Mathew327548c2017-07-13 15:19:51 +010018#define MAX_SPI_ID 1019
19
20#define TOTAL_SPI_INTR_NUM (MAX_SPI_ID - MIN_SPI_ID + 1)
21#define TOTAL_PCPU_INTR_NUM (MIN_SPI_ID - MIN_SGI_ID)
Achin Gupta92712a52015-09-03 14:18:02 +010022
23/* Mask for the priority field common to all GIC interfaces */
24#define GIC_PRI_MASK 0xff
25
Jeenu Viswambharan4684bce2017-09-22 08:32:09 +010026/* Mask for the configuration field common to all GIC interfaces */
27#define GIC_CFG_MASK 0x3
28
Achin Gupta92712a52015-09-03 14:18:02 +010029/* Constant to indicate a spurious interrupt in all GIC versions */
30#define GIC_SPURIOUS_INTERRUPT 1023
31
Jeenu Viswambharanb6982c02018-03-22 08:57:52 +000032/* Interrupt configurations: 2-bit fields with LSB reserved */
33#define GIC_INTR_CFG_LEVEL (0 << 1)
34#define GIC_INTR_CFG_EDGE (1 << 1)
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +010035
Achin Gupta92712a52015-09-03 14:18:02 +010036/* Constants to categorise priorities */
Jeenu Viswambharan6c6f24d2017-10-04 12:21:34 +010037#define GIC_HIGHEST_SEC_PRIORITY 0x0
38#define GIC_LOWEST_SEC_PRIORITY 0x7f
39#define GIC_HIGHEST_NS_PRIORITY 0x80
40#define GIC_LOWEST_NS_PRIORITY 0xfe /* 0xff would disable all interrupts */
Achin Gupta92712a52015-09-03 14:18:02 +010041
42/*******************************************************************************
43 * GIC Distributor interface register offsets that are common to GICv3 & GICv2
44 ******************************************************************************/
45#define GICD_CTLR 0x0
46#define GICD_TYPER 0x4
47#define GICD_IIDR 0x8
48#define GICD_IGROUPR 0x80
49#define GICD_ISENABLER 0x100
50#define GICD_ICENABLER 0x180
51#define GICD_ISPENDR 0x200
52#define GICD_ICPENDR 0x280
53#define GICD_ISACTIVER 0x300
54#define GICD_ICACTIVER 0x380
55#define GICD_IPRIORITYR 0x400
56#define GICD_ICFGR 0xc00
57#define GICD_NSACR 0xe00
58
59/* GICD_CTLR bit definitions */
60#define CTLR_ENABLE_G0_SHIFT 0
61#define CTLR_ENABLE_G0_MASK 0x1
62#define CTLR_ENABLE_G0_BIT (1 << CTLR_ENABLE_G0_SHIFT)
63
64
65/*******************************************************************************
66 * GIC Distributor interface register constants that are common to GICv3 & GICv2
67 ******************************************************************************/
68#define PIDR2_ARCH_REV_SHIFT 4
69#define PIDR2_ARCH_REV_MASK 0xf
70
71/* GICv3 revision as reported by the PIDR2 register */
72#define ARCH_REV_GICV3 0x3
73/* GICv2 revision as reported by the PIDR2 register */
74#define ARCH_REV_GICV2 0x2
Etienne Carriere0a8c3532017-11-05 22:57:38 +010075/* GICv1 revision as reported by the PIDR2 register */
76#define ARCH_REV_GICV1 0x1
Achin Gupta92712a52015-09-03 14:18:02 +010077
78#define IGROUPR_SHIFT 5
79#define ISENABLER_SHIFT 5
80#define ICENABLER_SHIFT ISENABLER_SHIFT
81#define ISPENDR_SHIFT 5
82#define ICPENDR_SHIFT ISPENDR_SHIFT
83#define ISACTIVER_SHIFT 5
84#define ICACTIVER_SHIFT ISACTIVER_SHIFT
85#define IPRIORITYR_SHIFT 2
Jeenu Viswambharandce70b32017-09-22 08:32:09 +010086#define ITARGETSR_SHIFT 2
Achin Gupta92712a52015-09-03 14:18:02 +010087#define ICFGR_SHIFT 4
88#define NSACR_SHIFT 4
89
90/* GICD_TYPER shifts and masks */
91#define TYPER_IT_LINES_NO_SHIFT 0
92#define TYPER_IT_LINES_NO_MASK 0x1f
93
94/* Value used to initialize Normal world interrupt priorities four at a time */
95#define GICD_IPRIORITYR_DEF_VAL \
96 (GIC_HIGHEST_NS_PRIORITY | \
97 (GIC_HIGHEST_NS_PRIORITY << 8) | \
98 (GIC_HIGHEST_NS_PRIORITY << 16) | \
99 (GIC_HIGHEST_NS_PRIORITY << 24))
100
Achin Gupta92712a52015-09-03 14:18:02 +0100101#endif /* __GIC_COMMON_H__ */