johpow01 | aef12f2 | 2020-10-15 13:40:04 -0500 | [diff] [blame] | 1 | /* |
Bipin Ravi | ad76713 | 2024-01-25 16:18:20 -0600 | [diff] [blame] | 2 | * Copyright (c) 2021-2024, Arm Limited. All rights reserved. |
johpow01 | aef12f2 | 2020-10-15 13:40:04 -0500 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <asm_macros.S> |
| 9 | #include <common/bl_common.h> |
Harrison Mutai | e5004c1 | 2023-05-23 17:28:03 +0100 | [diff] [blame] | 10 | #include <cortex_a715.h> |
johpow01 | aef12f2 | 2020-10-15 13:40:04 -0500 | [diff] [blame] | 11 | #include <cpu_macros.S> |
| 12 | #include <plat_macros.S> |
Bipin Ravi | 32464ba | 2022-05-06 16:02:30 -0500 | [diff] [blame] | 13 | #include "wa_cve_2022_23960_bhb_vector.S" |
johpow01 | aef12f2 | 2020-10-15 13:40:04 -0500 | [diff] [blame] | 14 | |
| 15 | /* Hardware handled coherency */ |
| 16 | #if HW_ASSISTED_COHERENCY == 0 |
Harrison Mutai | e5004c1 | 2023-05-23 17:28:03 +0100 | [diff] [blame] | 17 | #error "Cortex-A715 must be compiled with HW_ASSISTED_COHERENCY enabled" |
johpow01 | aef12f2 | 2020-10-15 13:40:04 -0500 | [diff] [blame] | 18 | #endif |
| 19 | |
| 20 | /* 64-bit only core */ |
| 21 | #if CTX_INCLUDE_AARCH32_REGS == 1 |
Harrison Mutai | e5004c1 | 2023-05-23 17:28:03 +0100 | [diff] [blame] | 22 | #error "Cortex-A715 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" |
johpow01 | aef12f2 | 2020-10-15 13:40:04 -0500 | [diff] [blame] | 23 | #endif |
| 24 | |
Bipin Ravi | 32464ba | 2022-05-06 16:02:30 -0500 | [diff] [blame] | 25 | #if WORKAROUND_CVE_2022_23960 |
Harrison Mutai | e5004c1 | 2023-05-23 17:28:03 +0100 | [diff] [blame] | 26 | wa_cve_2022_23960_bhb_vector_table CORTEX_A715_BHB_LOOP_COUNT, cortex_a715 |
Bipin Ravi | 32464ba | 2022-05-06 16:02:30 -0500 | [diff] [blame] | 27 | #endif /* WORKAROUND_CVE_2022_23960 */ |
| 28 | |
Bipin Ravi | a4ec940 | 2024-02-27 17:49:12 -0600 | [diff] [blame] | 29 | workaround_reset_start cortex_a715, ERRATUM(2331818), ERRATA_A715_2331818 |
| 30 | sysreg_bit_set CORTEX_A715_CPUACTLR2_EL1, BIT(20) |
| 31 | workaround_reset_end cortex_a715, ERRATUM(2331818) |
| 32 | |
| 33 | check_erratum_ls cortex_a715, ERRATUM(2331818), CPU_REV(1, 0) |
| 34 | |
Harrison Mutai | 5af4b78 | 2024-01-02 16:55:44 +0000 | [diff] [blame] | 35 | workaround_reset_start cortex_a715, ERRATUM(2344187), ERRATA_A715_2344187 |
| 36 | /* GCR_EL1 is only present with FEAT_MTE2. */ |
| 37 | mrs x1, ID_AA64PFR1_EL1 |
| 38 | ubfx x0, x1, ID_AA64PFR1_EL1_MTE_SHIFT, #4 |
| 39 | cmp x0, #MTE_IMPLEMENTED_ELX |
| 40 | bne #1f |
| 41 | sysreg_bit_set GCR_EL1, GCR_EL1_RRND_BIT |
| 42 | |
| 43 | 1: |
| 44 | /* Mitigation upon ERETAA and ERETAB. */ |
| 45 | mov x0, #2 |
| 46 | msr CORTEX_A715_CPUPSELR_EL3, x0 |
| 47 | isb |
| 48 | ldr x0, =0xd69f0bff |
| 49 | msr CORTEX_A715_CPUPOR_EL3, x0 |
| 50 | ldr x0, =0xfffffbff |
| 51 | msr CORTEX_A715_CPUPMR_EL3, x0 |
| 52 | mov x1, #0 |
| 53 | orr x1, x1, #(1<<0) |
| 54 | orr x1, x1, #(3<<4) |
| 55 | orr x1, x1, #(0xf<<6) |
| 56 | orr x1, x1, #(1<<13) |
| 57 | orr x1, x1, #(1<<53) |
| 58 | msr CORTEX_A715_CPUPCR_EL3, x1 |
| 59 | workaround_reset_end cortex_a715, ERRATUM(2344187) |
| 60 | |
| 61 | check_erratum_ls cortex_a715, ERRATUM(2344187), CPU_REV(1, 0) |
| 62 | |
Sona Mathew | bfcacc8 | 2024-02-20 16:59:45 -0600 | [diff] [blame] | 63 | workaround_reset_start cortex_a715, ERRATUM(2413290), ERRATA_A715_2413290 |
Sona Mathew | b6b812c | 2024-03-20 14:14:43 -0500 | [diff] [blame^] | 64 | /* Erratum 2413290 workaround is required only if SPE is enabled */ |
| 65 | #if ENABLE_SPE_FOR_NS != 0 |
| 66 | /* Check if Static profiling extension is implemented or present. */ |
Sona Mathew | bfcacc8 | 2024-02-20 16:59:45 -0600 | [diff] [blame] | 67 | mrs x1, id_aa64dfr0_el1 |
| 68 | ubfx x0, x1, ID_AA64DFR0_PMS_SHIFT, #4 |
| 69 | cbz x0, 1f |
Sona Mathew | b6b812c | 2024-03-20 14:14:43 -0500 | [diff] [blame^] | 70 | /* Apply the workaround by setting CPUACTLR_EL1[58:57] = 0b11. */ |
Sona Mathew | bfcacc8 | 2024-02-20 16:59:45 -0600 | [diff] [blame] | 71 | sysreg_bit_set CORTEX_A715_CPUACTLR_EL1, BIT(57) |
| 72 | sysreg_bit_set CORTEX_A715_CPUACTLR_EL1, BIT(58) |
| 73 | 1: |
Sona Mathew | b6b812c | 2024-03-20 14:14:43 -0500 | [diff] [blame^] | 74 | #endif |
Sona Mathew | bfcacc8 | 2024-02-20 16:59:45 -0600 | [diff] [blame] | 75 | workaround_reset_end cortex_a715, ERRATUM(2413290) |
| 76 | |
| 77 | check_erratum_range cortex_a715, ERRATUM(2413290), CPU_REV(1,0), CPU_REV(1, 0) |
| 78 | |
Bipin Ravi | 7ff2742 | 2024-02-27 17:34:05 -0600 | [diff] [blame] | 79 | workaround_reset_start cortex_a715, ERRATUM(2420947), ERRATA_A715_2420947 |
| 80 | sysreg_bit_set CORTEX_A715_CPUACTLR2_EL1, BIT(33) |
| 81 | workaround_reset_end cortex_a715, ERRATUM(2420947) |
| 82 | |
| 83 | check_erratum_range cortex_a715, ERRATUM(2420947), CPU_REV(1, 0), CPU_REV(1, 0) |
| 84 | |
Bipin Ravi | 9e7e008 | 2024-02-27 17:14:22 -0600 | [diff] [blame] | 85 | workaround_reset_start cortex_a715, ERRATUM(2429384), ERRATA_A715_2429384 |
| 86 | sysreg_bit_set CORTEX_A715_CPUACTLR2_EL1, BIT(27) |
| 87 | workaround_reset_end cortex_a715, ERRATUM(2429384) |
| 88 | |
| 89 | check_erratum_range cortex_a715, ERRATUM(2429384), CPU_REV(1, 0), CPU_REV(1, 0) |
| 90 | |
Bipin Ravi | d1d7932 | 2024-03-11 16:31:39 -0500 | [diff] [blame] | 91 | workaround_reset_start cortex_a715, ERRATUM(2561034), ERRATA_A715_2561034 |
Bipin Ravi | ad76713 | 2024-01-25 16:18:20 -0600 | [diff] [blame] | 92 | sysreg_bit_set CORTEX_A715_CPUACTLR2_EL1, BIT(26) |
Bipin Ravi | d1d7932 | 2024-03-11 16:31:39 -0500 | [diff] [blame] | 93 | workaround_reset_end cortex_a715, ERRATUM(2561034) |
Bipin Ravi | ad76713 | 2024-01-25 16:18:20 -0600 | [diff] [blame] | 94 | |
| 95 | check_erratum_range cortex_a715, ERRATUM(2561034), CPU_REV(1, 0), CPU_REV(1, 0) |
| 96 | |
Harrison Mutai | cb50c11 | 2023-05-04 18:15:16 +0100 | [diff] [blame] | 97 | workaround_reset_start cortex_a715, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 |
| 98 | #if IMAGE_BL31 |
Bipin Ravi | 32464ba | 2022-05-06 16:02:30 -0500 | [diff] [blame] | 99 | /* |
Harrison Mutai | e5004c1 | 2023-05-23 17:28:03 +0100 | [diff] [blame] | 100 | * The Cortex-A715 generic vectors are overridden to apply errata |
Bipin Ravi | 32464ba | 2022-05-06 16:02:30 -0500 | [diff] [blame] | 101 | * mitigation on exception entry from lower ELs. |
| 102 | */ |
Harrison Mutai | cb50c11 | 2023-05-04 18:15:16 +0100 | [diff] [blame] | 103 | override_vector_table wa_cve_vbar_cortex_a715 |
| 104 | #endif /* IMAGE_BL31 */ |
| 105 | workaround_reset_end cortex_a715, CVE(2022, 23960) |
Bipin Ravi | 32464ba | 2022-05-06 16:02:30 -0500 | [diff] [blame] | 106 | |
Harrison Mutai | cb50c11 | 2023-05-04 18:15:16 +0100 | [diff] [blame] | 107 | check_erratum_chosen cortex_a715, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 |
| 108 | |
| 109 | cpu_reset_func_start cortex_a715 |
| 110 | /* Disable speculative loads */ |
| 111 | msr SSBS, xzr |
| 112 | cpu_reset_func_end cortex_a715 |
johpow01 | aef12f2 | 2020-10-15 13:40:04 -0500 | [diff] [blame] | 113 | |
| 114 | /* ---------------------------------------------------- |
| 115 | * HW will do the cache maintenance while powering down |
| 116 | * ---------------------------------------------------- |
| 117 | */ |
Harrison Mutai | e5004c1 | 2023-05-23 17:28:03 +0100 | [diff] [blame] | 118 | func cortex_a715_core_pwr_dwn |
johpow01 | aef12f2 | 2020-10-15 13:40:04 -0500 | [diff] [blame] | 119 | /* --------------------------------------------------- |
| 120 | * Enable CPU power down bit in power control register |
| 121 | * --------------------------------------------------- |
| 122 | */ |
Harrison Mutai | e5004c1 | 2023-05-23 17:28:03 +0100 | [diff] [blame] | 123 | mrs x0, CORTEX_A715_CPUPWRCTLR_EL1 |
| 124 | orr x0, x0, #CORTEX_A715_CPUPWRCTLR_EL1_CORE_PWRDN_BIT |
| 125 | msr CORTEX_A715_CPUPWRCTLR_EL1, x0 |
johpow01 | aef12f2 | 2020-10-15 13:40:04 -0500 | [diff] [blame] | 126 | isb |
| 127 | ret |
Harrison Mutai | e5004c1 | 2023-05-23 17:28:03 +0100 | [diff] [blame] | 128 | endfunc cortex_a715_core_pwr_dwn |
johpow01 | aef12f2 | 2020-10-15 13:40:04 -0500 | [diff] [blame] | 129 | |
Harrison Mutai | cb50c11 | 2023-05-04 18:15:16 +0100 | [diff] [blame] | 130 | errata_report_shim cortex_a715 |
johpow01 | aef12f2 | 2020-10-15 13:40:04 -0500 | [diff] [blame] | 131 | |
| 132 | /* --------------------------------------------- |
Harrison Mutai | e5004c1 | 2023-05-23 17:28:03 +0100 | [diff] [blame] | 133 | * This function provides Cortex-A715 specific |
johpow01 | aef12f2 | 2020-10-15 13:40:04 -0500 | [diff] [blame] | 134 | * register information for crash reporting. |
| 135 | * It needs to return with x6 pointing to |
| 136 | * a list of register names in ascii and |
| 137 | * x8 - x15 having values of registers to be |
| 138 | * reported. |
| 139 | * --------------------------------------------- |
| 140 | */ |
Harrison Mutai | e5004c1 | 2023-05-23 17:28:03 +0100 | [diff] [blame] | 141 | .section .rodata.cortex_a715_regs, "aS" |
| 142 | cortex_a715_regs: /* The ascii list of register names to be reported */ |
johpow01 | aef12f2 | 2020-10-15 13:40:04 -0500 | [diff] [blame] | 143 | .asciz "cpuectlr_el1", "" |
| 144 | |
Harrison Mutai | e5004c1 | 2023-05-23 17:28:03 +0100 | [diff] [blame] | 145 | func cortex_a715_cpu_reg_dump |
| 146 | adr x6, cortex_a715_regs |
| 147 | mrs x8, CORTEX_A715_CPUECTLR_EL1 |
johpow01 | aef12f2 | 2020-10-15 13:40:04 -0500 | [diff] [blame] | 148 | ret |
Harrison Mutai | e5004c1 | 2023-05-23 17:28:03 +0100 | [diff] [blame] | 149 | endfunc cortex_a715_cpu_reg_dump |
johpow01 | aef12f2 | 2020-10-15 13:40:04 -0500 | [diff] [blame] | 150 | |
Harrison Mutai | e5004c1 | 2023-05-23 17:28:03 +0100 | [diff] [blame] | 151 | declare_cpu_ops cortex_a715, CORTEX_A715_MIDR, \ |
| 152 | cortex_a715_reset_func, \ |
| 153 | cortex_a715_core_pwr_dwn |