commit 7ff274228e08b929600e673bce99f572f15131c0
author Bipin Ravi <biprav01@u203721.austin.arm.com> Tue Feb 27 17:34:05 2024 -0600
committer Bipin Ravi <biprav01@u203721.austin.arm.com> Wed Mar 06 13:10:31 2024 -0600
tree 19cf0171225fa33bc6d193865067888edc0fd710
parent 455ff2e1f0a0fa73829332be747d79513aac92e7

fix(cpus): workaround for Cortex-A715 erratum 2420947

Cortex-A715 erratum 2420947 is a cat B erratum that applies only
to revision r1p0 and is fixed in r1p1. The workaround is to set
bit[33] of CPUACTLR2_EL1. This will prevent store and store-release
to merge inside the write buffer, and it is not expected to have
much performance impacts.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN2148827/latest

Change-Id: I01a71b878cd958e742ff8357f8cdfbfc5625de47
Signed-off-by: Bipin Ravi <biprav01@u203721.austin.arm.com>

lib/cpus/aarch64/cortex_a715.S

diff --git a/lib/cpus/aarch64/cortex_a715.S b/lib/cpus/aarch64/cortex_a715.S
index 44796b6..a9bb370 100644
--- a/lib/cpus/aarch64/cortex_a715.S
+++ b/lib/cpus/aarch64/cortex_a715.S
@@ -26,6 +26,12 @@
 	wa_cve_2022_23960_bhb_vector_table CORTEX_A715_BHB_LOOP_COUNT, cortex_a715
 #endif /* WORKAROUND_CVE_2022_23960 */
 
+workaround_reset_start cortex_a715, ERRATUM(2420947), ERRATA_A715_2420947
+        sysreg_bit_set CORTEX_A715_CPUACTLR2_EL1, BIT(33)
+workaround_reset_end cortex_a715, ERRATUM(2420947)
+
+check_erratum_range cortex_a715, ERRATUM(2420947), CPU_REV(1, 0), CPU_REV(1, 0)
+
 workaround_reset_start cortex_a715, ERRATUM(2429384), ERRATA_A715_2429384
         sysreg_bit_set CORTEX_A715_CPUACTLR2_EL1, BIT(27)
 workaround_reset_end cortex_a715, ERRATUM(2429384)