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Yatharth Kocharf528faf2016-06-28 16:58:26 +01001/*
Dimitris Papastamos0a4cded2018-01-02 11:37:02 +00002 * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
Yatharth Kocharf528faf2016-06-28 16:58:26 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Yatharth Kocharf528faf2016-06-28 16:58:26 +01005 */
6
7#ifndef __EL3_COMMON_MACROS_S__
8#define __EL3_COMMON_MACROS_S__
9
10#include <arch.h>
11#include <asm_macros.S>
12#include <assert_macros.S>
13
14 /*
15 * Helper macro to initialise EL3 registers we care about.
16 */
Dimitris Papastamos0a4cded2018-01-02 11:37:02 +000017 .macro el3_arch_init_common
Yatharth Kocharf528faf2016-06-28 16:58:26 +010018 /* ---------------------------------------------------------------------
David Cunadofee86532017-04-13 22:38:29 +010019 * SCTLR has already been initialised - read current value before
20 * modifying.
21 *
22 * SCTLR.I: Enable the instruction cache.
23 *
24 * SCTLR.A: Enable Alignment fault checking. All instructions that load
25 * or store one or more registers have an alignment check that the
26 * address being accessed is aligned to the size of the data element(s)
27 * being accessed.
Yatharth Kocharf528faf2016-06-28 16:58:26 +010028 * ---------------------------------------------------------------------
29 */
David Cunadofee86532017-04-13 22:38:29 +010030 ldr r1, =(SCTLR_I_BIT | SCTLR_A_BIT)
Yatharth Kocharf528faf2016-06-28 16:58:26 +010031 ldcopr r0, SCTLR
32 orr r0, r0, r1
33 stcopr r0, SCTLR
34 isb
35
36 /* ---------------------------------------------------------------------
David Cunadofee86532017-04-13 22:38:29 +010037 * Initialise SCR, setting all fields rather than relying on the hw.
38 *
39 * SCR.SIF: Enabled so that Secure state instruction fetches from
40 * Non-secure memory are not permitted.
41 * ---------------------------------------------------------------------
Yatharth Kocharf528faf2016-06-28 16:58:26 +010042 */
David Cunadofee86532017-04-13 22:38:29 +010043 ldr r0, =(SCR_RESET_VAL | SCR_SIF_BIT)
Yatharth Kocharf528faf2016-06-28 16:58:26 +010044 stcopr r0, SCR
45
46 /* -----------------------------------------------------
47 * Enable the Asynchronous data abort now that the
48 * exception vectors have been setup.
49 * -----------------------------------------------------
50 */
51 cpsie a
52 isb
53
David Cunadofee86532017-04-13 22:38:29 +010054 /* ---------------------------------------------------------------------
55 * Initialise NSACR, setting all the fields, except for the
56 * IMPLEMENTATION DEFINED field, rather than relying on the hw. Some
57 * fields are architecturally UNKNOWN on reset.
58 *
59 * NSACR_ENABLE_FP_ACCESS: Represents NSACR.cp11 and NSACR.cp10. The
60 * cp11 field is ignored, but is set to same value as cp10. The cp10
61 * field is set to allow access to Advanced SIMD and floating point
62 * features from both Security states.
63 * ---------------------------------------------------------------------
64 */
Yatharth Kocharf528faf2016-06-28 16:58:26 +010065 ldcopr r0, NSACR
David Cunadofee86532017-04-13 22:38:29 +010066 and r0, r0, #NSACR_IMP_DEF_MASK
67 orr r0, r0, #(NSACR_RESET_VAL | NSACR_ENABLE_FP_ACCESS)
Yatharth Kocharf528faf2016-06-28 16:58:26 +010068 stcopr r0, NSACR
69 isb
70
David Cunadofee86532017-04-13 22:38:29 +010071 /* ---------------------------------------------------------------------
72 * Initialise CPACR, setting all fields rather than relying on hw. Some
73 * fields are architecturally UNKNOWN on reset.
74 *
75 * CPACR.TRCDIS: Trap control for PL0 and PL1 System register accesses
76 * to trace registers. Set to zero to allow access.
77 *
78 * CPACR_ENABLE_FP_ACCESS: Represents CPACR.cp11 and CPACR.cp10. The
79 * cp11 field is ignored, but is set to same value as cp10. The cp10
80 * field is set to allow full access from PL0 and PL1 to floating-point
81 * and Advanced SIMD features.
82 * ---------------------------------------------------------------------
Yatharth Kocharf528faf2016-06-28 16:58:26 +010083 */
David Cunadofee86532017-04-13 22:38:29 +010084 ldr r0, =((CPACR_RESET_VAL | CPACR_ENABLE_FP_ACCESS) & ~(TRCDIS_BIT))
Yatharth Kocharf528faf2016-06-28 16:58:26 +010085 stcopr r0, CPACR
86 isb
87
David Cunadofee86532017-04-13 22:38:29 +010088 /* ---------------------------------------------------------------------
89 * Initialise FPEXC, setting all fields rather than relying on hw. Some
90 * fields are architecturally UNKNOWN on reset and are set to zero
91 * except for field(s) listed below.
92 *
93 * FPEXC.EN: Enable access to Advanced SIMD and floating point features
94 * from all exception levels.
95 * ---------------------------------------------------------------------
96 */
97 ldr r0, =(FPEXC_RESET_VAL | FPEXC_EN_BIT)
Yatharth Kocharf528faf2016-06-28 16:58:26 +010098 vmsr FPEXC, r0
99 isb
dp-arm595d0d52017-02-08 11:51:50 +0000100
Etienne Carriere863858b2017-11-05 22:55:55 +0100101#if (ARM_ARCH_MAJOR > 7)
David Cunadofee86532017-04-13 22:38:29 +0100102 /* ---------------------------------------------------------------------
103 * Initialise SDCR, setting all the fields rather than relying on hw.
104 *
105 * SDCR.SPD: Disable AArch32 privileged debug. Debug exceptions from
106 * Secure EL1 are disabled.
107 * ---------------------------------------------------------------------
108 */
109 ldr r0, =(SDCR_RESET_VAL | SDCR_SPD(SDCR_SPD_DISABLE))
dp-arm595d0d52017-02-08 11:51:50 +0000110 stcopr r0, SDCR
Etienne Carriere863858b2017-11-05 22:55:55 +0100111#endif
dp-arm595d0d52017-02-08 11:51:50 +0000112
Yatharth Kocharf528faf2016-06-28 16:58:26 +0100113 .endm
114
115/* -----------------------------------------------------------------------------
116 * This is the super set of actions that need to be performed during a cold boot
117 * or a warm boot in EL3. This code is shared by BL1 and BL32 (SP_MIN).
118 *
119 * This macro will always perform reset handling, architectural initialisations
120 * and stack setup. The rest of the actions are optional because they might not
121 * be needed, depending on the context in which this macro is called. This is
122 * why this macro is parameterised ; each parameter allows to enable/disable
123 * some actions.
124 *
David Cunadofee86532017-04-13 22:38:29 +0100125 * _init_sctlr:
126 * Whether the macro needs to initialise the SCTLR register including
127 * configuring the endianness of data accesses.
Yatharth Kocharf528faf2016-06-28 16:58:26 +0100128 *
129 * _warm_boot_mailbox:
130 * Whether the macro needs to detect the type of boot (cold/warm). The
131 * detection is based on the platform entrypoint address : if it is zero
132 * then it is a cold boot, otherwise it is a warm boot. In the latter case,
133 * this macro jumps on the platform entrypoint address.
134 *
135 * _secondary_cold_boot:
136 * Whether the macro needs to identify the CPU that is calling it: primary
137 * CPU or secondary CPU. The primary CPU will be allowed to carry on with
138 * the platform initialisations, while the secondaries will be put in a
139 * platform-specific state in the meantime.
140 *
141 * If the caller knows this macro will only be called by the primary CPU
142 * then this parameter can be defined to 0 to skip this step.
143 *
144 * _init_memory:
145 * Whether the macro needs to initialise the memory.
146 *
147 * _init_c_runtime:
148 * Whether the macro needs to initialise the C runtime environment.
149 *
150 * _exception_vectors:
151 * Address of the exception vectors to program in the VBAR_EL3 register.
152 * -----------------------------------------------------------------------------
153 */
154 .macro el3_entrypoint_common \
David Cunadofee86532017-04-13 22:38:29 +0100155 _init_sctlr, _warm_boot_mailbox, _secondary_cold_boot, \
Yatharth Kocharf528faf2016-06-28 16:58:26 +0100156 _init_memory, _init_c_runtime, _exception_vectors
157
158 /* Make sure we are in Secure Mode */
Antonio Nino Diaz7c65c1e2017-04-20 09:58:28 +0100159#if ENABLE_ASSERTIONS
Yatharth Kocharf528faf2016-06-28 16:58:26 +0100160 ldcopr r0, SCR
161 tst r0, #SCR_NS_BIT
162 ASM_ASSERT(eq)
163#endif
164
David Cunadofee86532017-04-13 22:38:29 +0100165 .if \_init_sctlr
Yatharth Kocharf528faf2016-06-28 16:58:26 +0100166 /* -------------------------------------------------------------
David Cunadofee86532017-04-13 22:38:29 +0100167 * This is the initialisation of SCTLR and so must ensure that
168 * all fields are explicitly set rather than relying on hw. Some
169 * fields reset to an IMPLEMENTATION DEFINED value.
170 *
171 * SCTLR.TE: Set to zero so that exceptions to an Exception
172 * Level executing at PL1 are taken to A32 state.
173 *
174 * SCTLR.EE: Set the CPU endianness before doing anything that
175 * might involve memory reads or writes. Set to zero to select
176 * Little Endian.
177 *
178 * SCTLR.V: Set to zero to select the normal exception vectors
179 * with base address held in VBAR.
Yatharth Kocharf528faf2016-06-28 16:58:26 +0100180 * -------------------------------------------------------------
181 */
David Cunadofee86532017-04-13 22:38:29 +0100182 ldr r0, =(SCTLR_RESET_VAL & ~(SCTLR_TE_BIT | SCTLR_EE_BIT | SCTLR_V_BIT))
Yatharth Kocharf528faf2016-06-28 16:58:26 +0100183 stcopr r0, SCTLR
184 isb
David Cunadofee86532017-04-13 22:38:29 +0100185 .endif /* _init_sctlr */
Yatharth Kocharf528faf2016-06-28 16:58:26 +0100186
187 /* Switch to monitor mode */
188 cps #MODE32_mon
189 isb
190
191 .if \_warm_boot_mailbox
192 /* -------------------------------------------------------------
193 * This code will be executed for both warm and cold resets.
194 * Now is the time to distinguish between the two.
195 * Query the platform entrypoint address and if it is not zero
196 * then it means it is a warm boot so jump to this address.
197 * -------------------------------------------------------------
198 */
199 bl plat_get_my_entrypoint
200 cmp r0, #0
201 bxne r0
202 .endif /* _warm_boot_mailbox */
203
204 /* ---------------------------------------------------------------------
Dimitris Papastamos0a4cded2018-01-02 11:37:02 +0000205 * Set the exception vectors (VBAR/MVBAR).
206 * ---------------------------------------------------------------------
207 */
208 ldr r0, =\_exception_vectors
209 stcopr r0, VBAR
210 stcopr r0, MVBAR
211 isb
212
213 /* ---------------------------------------------------------------------
Yatharth Kocharf528faf2016-06-28 16:58:26 +0100214 * It is a cold boot.
215 * Perform any processor specific actions upon reset e.g. cache, TLB
216 * invalidations etc.
217 * ---------------------------------------------------------------------
218 */
219 bl reset_handler
220
Dimitris Papastamos0a4cded2018-01-02 11:37:02 +0000221 el3_arch_init_common
Yatharth Kocharf528faf2016-06-28 16:58:26 +0100222
223 .if \_secondary_cold_boot
224 /* -------------------------------------------------------------
225 * Check if this is a primary or secondary CPU cold boot.
226 * The primary CPU will set up the platform while the
227 * secondaries are placed in a platform-specific state until the
228 * primary CPU performs the necessary actions to bring them out
229 * of that state and allows entry into the OS.
230 * -------------------------------------------------------------
231 */
232 bl plat_is_my_cpu_primary
233 cmp r0, #0
234 bne do_primary_cold_boot
235
236 /* This is a cold boot on a secondary CPU */
237 bl plat_secondary_cold_boot_setup
238 /* plat_secondary_cold_boot_setup() is not supposed to return */
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000239 no_ret plat_panic_handler
Yatharth Kocharf528faf2016-06-28 16:58:26 +0100240
241 do_primary_cold_boot:
242 .endif /* _secondary_cold_boot */
243
244 /* ---------------------------------------------------------------------
245 * Initialize memory now. Secondary CPU initialization won't get to this
246 * point.
247 * ---------------------------------------------------------------------
248 */
249
250 .if \_init_memory
251 bl platform_mem_init
252 .endif /* _init_memory */
253
254 /* ---------------------------------------------------------------------
255 * Init C runtime environment:
256 * - Zero-initialise the NOBITS sections. There are 2 of them:
257 * - the .bss section;
258 * - the coherent memory section (if any).
259 * - Relocate the data section from ROM to RAM, if required.
260 * ---------------------------------------------------------------------
261 */
262 .if \_init_c_runtime
Roberto Vargase0e99462017-10-30 14:43:43 +0000263#if defined(IMAGE_BL32) || (defined(IMAGE_BL2) && BL2_AT_EL3)
Yatharth Kocharf528faf2016-06-28 16:58:26 +0100264 /* -----------------------------------------------------------------
Roberto Vargase0e99462017-10-30 14:43:43 +0000265 * Invalidate the RW memory used by the image. This
Yatharth Kocharf528faf2016-06-28 16:58:26 +0100266 * includes the data and NOBITS sections. This is done to
267 * safeguard against possible corruption of this memory by
268 * dirty cache lines in a system cache as a result of use by
269 * an earlier boot loader stage.
270 * -----------------------------------------------------------------
271 */
272 ldr r0, =__RW_START__
273 ldr r1, =__RW_END__
274 sub r1, r1, r0
275 bl inv_dcache_range
Roberto Vargase0e99462017-10-30 14:43:43 +0000276#endif
Yatharth Kocharf528faf2016-06-28 16:58:26 +0100277
278 ldr r0, =__BSS_START__
279 ldr r1, =__BSS_SIZE__
280 bl zeromem
281
282#if USE_COHERENT_MEM
283 ldr r0, =__COHERENT_RAM_START__
284 ldr r1, =__COHERENT_RAM_UNALIGNED_SIZE__
285 bl zeromem
286#endif
287
Masahiro Yamada441bfdd2016-12-25 23:36:24 +0900288#ifdef IMAGE_BL1
Yatharth Kocharf528faf2016-06-28 16:58:26 +0100289 /* -----------------------------------------------------
290 * Copy data from ROM to RAM.
291 * -----------------------------------------------------
292 */
293 ldr r0, =__DATA_RAM_START__
294 ldr r1, =__DATA_ROM_START__
295 ldr r2, =__DATA_SIZE__
Yatharth Kocharc44c5af2016-09-28 11:00:05 +0100296 bl memcpy4
Yatharth Kocharf528faf2016-06-28 16:58:26 +0100297#endif
298 .endif /* _init_c_runtime */
299
300 /* ---------------------------------------------------------------------
301 * Allocate a stack whose memory will be marked as Normal-IS-WBWA when
302 * the MMU is enabled. There is no risk of reading stale stack memory
303 * after enabling the MMU as only the primary CPU is running at the
304 * moment.
305 * ---------------------------------------------------------------------
306 */
307 bl plat_set_my_stack
Douglas Raillard306593d2017-02-24 18:14:15 +0000308
309#if STACK_PROTECTOR_ENABLED
310 .if \_init_c_runtime
311 bl update_stack_protector_canary
312 .endif /* _init_c_runtime */
313#endif
Yatharth Kocharf528faf2016-06-28 16:58:26 +0100314 .endm
315
316#endif /* __EL3_COMMON_MACROS_S__ */