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Yatharth Kocharf528faf2016-06-28 16:58:26 +01001/*
Douglas Raillard306593d2017-02-24 18:14:15 +00002 * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
Yatharth Kocharf528faf2016-06-28 16:58:26 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Yatharth Kocharf528faf2016-06-28 16:58:26 +01005 */
6
7#ifndef __EL3_COMMON_MACROS_S__
8#define __EL3_COMMON_MACROS_S__
9
10#include <arch.h>
11#include <asm_macros.S>
12#include <assert_macros.S>
13
14 /*
15 * Helper macro to initialise EL3 registers we care about.
16 */
17 .macro el3_arch_init_common _exception_vectors
18 /* ---------------------------------------------------------------------
David Cunadofee86532017-04-13 22:38:29 +010019 * SCTLR has already been initialised - read current value before
20 * modifying.
21 *
22 * SCTLR.I: Enable the instruction cache.
23 *
24 * SCTLR.A: Enable Alignment fault checking. All instructions that load
25 * or store one or more registers have an alignment check that the
26 * address being accessed is aligned to the size of the data element(s)
27 * being accessed.
Yatharth Kocharf528faf2016-06-28 16:58:26 +010028 * ---------------------------------------------------------------------
29 */
David Cunadofee86532017-04-13 22:38:29 +010030 ldr r1, =(SCTLR_I_BIT | SCTLR_A_BIT)
Yatharth Kocharf528faf2016-06-28 16:58:26 +010031 ldcopr r0, SCTLR
32 orr r0, r0, r1
33 stcopr r0, SCTLR
34 isb
35
36 /* ---------------------------------------------------------------------
37 * Set the exception vectors (VBAR/MVBAR).
38 * ---------------------------------------------------------------------
39 */
40 ldr r0, =\_exception_vectors
41 stcopr r0, VBAR
42 stcopr r0, MVBAR
43 isb
44
David Cunadofee86532017-04-13 22:38:29 +010045 /* ---------------------------------------------------------------------
46 * Initialise SCR, setting all fields rather than relying on the hw.
47 *
48 * SCR.SIF: Enabled so that Secure state instruction fetches from
49 * Non-secure memory are not permitted.
50 * ---------------------------------------------------------------------
Yatharth Kocharf528faf2016-06-28 16:58:26 +010051 */
David Cunadofee86532017-04-13 22:38:29 +010052 ldr r0, =(SCR_RESET_VAL | SCR_SIF_BIT)
Yatharth Kocharf528faf2016-06-28 16:58:26 +010053 stcopr r0, SCR
54
55 /* -----------------------------------------------------
56 * Enable the Asynchronous data abort now that the
57 * exception vectors have been setup.
58 * -----------------------------------------------------
59 */
60 cpsie a
61 isb
62
David Cunadofee86532017-04-13 22:38:29 +010063 /* ---------------------------------------------------------------------
64 * Initialise NSACR, setting all the fields, except for the
65 * IMPLEMENTATION DEFINED field, rather than relying on the hw. Some
66 * fields are architecturally UNKNOWN on reset.
67 *
68 * NSACR_ENABLE_FP_ACCESS: Represents NSACR.cp11 and NSACR.cp10. The
69 * cp11 field is ignored, but is set to same value as cp10. The cp10
70 * field is set to allow access to Advanced SIMD and floating point
71 * features from both Security states.
72 * ---------------------------------------------------------------------
73 */
Yatharth Kocharf528faf2016-06-28 16:58:26 +010074 ldcopr r0, NSACR
David Cunadofee86532017-04-13 22:38:29 +010075 and r0, r0, #NSACR_IMP_DEF_MASK
76 orr r0, r0, #(NSACR_RESET_VAL | NSACR_ENABLE_FP_ACCESS)
Yatharth Kocharf528faf2016-06-28 16:58:26 +010077 stcopr r0, NSACR
78 isb
79
David Cunadofee86532017-04-13 22:38:29 +010080 /* ---------------------------------------------------------------------
81 * Initialise CPACR, setting all fields rather than relying on hw. Some
82 * fields are architecturally UNKNOWN on reset.
83 *
84 * CPACR.TRCDIS: Trap control for PL0 and PL1 System register accesses
85 * to trace registers. Set to zero to allow access.
86 *
87 * CPACR_ENABLE_FP_ACCESS: Represents CPACR.cp11 and CPACR.cp10. The
88 * cp11 field is ignored, but is set to same value as cp10. The cp10
89 * field is set to allow full access from PL0 and PL1 to floating-point
90 * and Advanced SIMD features.
91 * ---------------------------------------------------------------------
Yatharth Kocharf528faf2016-06-28 16:58:26 +010092 */
David Cunadofee86532017-04-13 22:38:29 +010093 ldr r0, =((CPACR_RESET_VAL | CPACR_ENABLE_FP_ACCESS) & ~(TRCDIS_BIT))
Yatharth Kocharf528faf2016-06-28 16:58:26 +010094 stcopr r0, CPACR
95 isb
96
David Cunadofee86532017-04-13 22:38:29 +010097 /* ---------------------------------------------------------------------
98 * Initialise FPEXC, setting all fields rather than relying on hw. Some
99 * fields are architecturally UNKNOWN on reset and are set to zero
100 * except for field(s) listed below.
101 *
102 * FPEXC.EN: Enable access to Advanced SIMD and floating point features
103 * from all exception levels.
104 * ---------------------------------------------------------------------
105 */
106 ldr r0, =(FPEXC_RESET_VAL | FPEXC_EN_BIT)
Yatharth Kocharf528faf2016-06-28 16:58:26 +0100107 vmsr FPEXC, r0
108 isb
dp-arm595d0d52017-02-08 11:51:50 +0000109
Etienne Carriere863858b2017-11-05 22:55:55 +0100110#if (ARM_ARCH_MAJOR > 7)
David Cunadofee86532017-04-13 22:38:29 +0100111 /* ---------------------------------------------------------------------
112 * Initialise SDCR, setting all the fields rather than relying on hw.
113 *
114 * SDCR.SPD: Disable AArch32 privileged debug. Debug exceptions from
115 * Secure EL1 are disabled.
116 * ---------------------------------------------------------------------
117 */
118 ldr r0, =(SDCR_RESET_VAL | SDCR_SPD(SDCR_SPD_DISABLE))
dp-arm595d0d52017-02-08 11:51:50 +0000119 stcopr r0, SDCR
Etienne Carriere863858b2017-11-05 22:55:55 +0100120#endif
dp-arm595d0d52017-02-08 11:51:50 +0000121
Yatharth Kocharf528faf2016-06-28 16:58:26 +0100122 .endm
123
124/* -----------------------------------------------------------------------------
125 * This is the super set of actions that need to be performed during a cold boot
126 * or a warm boot in EL3. This code is shared by BL1 and BL32 (SP_MIN).
127 *
128 * This macro will always perform reset handling, architectural initialisations
129 * and stack setup. The rest of the actions are optional because they might not
130 * be needed, depending on the context in which this macro is called. This is
131 * why this macro is parameterised ; each parameter allows to enable/disable
132 * some actions.
133 *
David Cunadofee86532017-04-13 22:38:29 +0100134 * _init_sctlr:
135 * Whether the macro needs to initialise the SCTLR register including
136 * configuring the endianness of data accesses.
Yatharth Kocharf528faf2016-06-28 16:58:26 +0100137 *
138 * _warm_boot_mailbox:
139 * Whether the macro needs to detect the type of boot (cold/warm). The
140 * detection is based on the platform entrypoint address : if it is zero
141 * then it is a cold boot, otherwise it is a warm boot. In the latter case,
142 * this macro jumps on the platform entrypoint address.
143 *
144 * _secondary_cold_boot:
145 * Whether the macro needs to identify the CPU that is calling it: primary
146 * CPU or secondary CPU. The primary CPU will be allowed to carry on with
147 * the platform initialisations, while the secondaries will be put in a
148 * platform-specific state in the meantime.
149 *
150 * If the caller knows this macro will only be called by the primary CPU
151 * then this parameter can be defined to 0 to skip this step.
152 *
153 * _init_memory:
154 * Whether the macro needs to initialise the memory.
155 *
156 * _init_c_runtime:
157 * Whether the macro needs to initialise the C runtime environment.
158 *
159 * _exception_vectors:
160 * Address of the exception vectors to program in the VBAR_EL3 register.
161 * -----------------------------------------------------------------------------
162 */
163 .macro el3_entrypoint_common \
David Cunadofee86532017-04-13 22:38:29 +0100164 _init_sctlr, _warm_boot_mailbox, _secondary_cold_boot, \
Yatharth Kocharf528faf2016-06-28 16:58:26 +0100165 _init_memory, _init_c_runtime, _exception_vectors
166
167 /* Make sure we are in Secure Mode */
Antonio Nino Diaz7c65c1e2017-04-20 09:58:28 +0100168#if ENABLE_ASSERTIONS
Yatharth Kocharf528faf2016-06-28 16:58:26 +0100169 ldcopr r0, SCR
170 tst r0, #SCR_NS_BIT
171 ASM_ASSERT(eq)
172#endif
173
David Cunadofee86532017-04-13 22:38:29 +0100174 .if \_init_sctlr
Yatharth Kocharf528faf2016-06-28 16:58:26 +0100175 /* -------------------------------------------------------------
David Cunadofee86532017-04-13 22:38:29 +0100176 * This is the initialisation of SCTLR and so must ensure that
177 * all fields are explicitly set rather than relying on hw. Some
178 * fields reset to an IMPLEMENTATION DEFINED value.
179 *
180 * SCTLR.TE: Set to zero so that exceptions to an Exception
181 * Level executing at PL1 are taken to A32 state.
182 *
183 * SCTLR.EE: Set the CPU endianness before doing anything that
184 * might involve memory reads or writes. Set to zero to select
185 * Little Endian.
186 *
187 * SCTLR.V: Set to zero to select the normal exception vectors
188 * with base address held in VBAR.
Yatharth Kocharf528faf2016-06-28 16:58:26 +0100189 * -------------------------------------------------------------
190 */
David Cunadofee86532017-04-13 22:38:29 +0100191 ldr r0, =(SCTLR_RESET_VAL & ~(SCTLR_TE_BIT | SCTLR_EE_BIT | SCTLR_V_BIT))
Yatharth Kocharf528faf2016-06-28 16:58:26 +0100192 stcopr r0, SCTLR
193 isb
David Cunadofee86532017-04-13 22:38:29 +0100194 .endif /* _init_sctlr */
Yatharth Kocharf528faf2016-06-28 16:58:26 +0100195
196 /* Switch to monitor mode */
197 cps #MODE32_mon
198 isb
199
200 .if \_warm_boot_mailbox
201 /* -------------------------------------------------------------
202 * This code will be executed for both warm and cold resets.
203 * Now is the time to distinguish between the two.
204 * Query the platform entrypoint address and if it is not zero
205 * then it means it is a warm boot so jump to this address.
206 * -------------------------------------------------------------
207 */
208 bl plat_get_my_entrypoint
209 cmp r0, #0
210 bxne r0
211 .endif /* _warm_boot_mailbox */
212
213 /* ---------------------------------------------------------------------
214 * It is a cold boot.
215 * Perform any processor specific actions upon reset e.g. cache, TLB
216 * invalidations etc.
217 * ---------------------------------------------------------------------
218 */
219 bl reset_handler
220
221 el3_arch_init_common \_exception_vectors
222
223 .if \_secondary_cold_boot
224 /* -------------------------------------------------------------
225 * Check if this is a primary or secondary CPU cold boot.
226 * The primary CPU will set up the platform while the
227 * secondaries are placed in a platform-specific state until the
228 * primary CPU performs the necessary actions to bring them out
229 * of that state and allows entry into the OS.
230 * -------------------------------------------------------------
231 */
232 bl plat_is_my_cpu_primary
233 cmp r0, #0
234 bne do_primary_cold_boot
235
236 /* This is a cold boot on a secondary CPU */
237 bl plat_secondary_cold_boot_setup
238 /* plat_secondary_cold_boot_setup() is not supposed to return */
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000239 no_ret plat_panic_handler
Yatharth Kocharf528faf2016-06-28 16:58:26 +0100240
241 do_primary_cold_boot:
242 .endif /* _secondary_cold_boot */
243
244 /* ---------------------------------------------------------------------
245 * Initialize memory now. Secondary CPU initialization won't get to this
246 * point.
247 * ---------------------------------------------------------------------
248 */
249
250 .if \_init_memory
251 bl platform_mem_init
252 .endif /* _init_memory */
253
254 /* ---------------------------------------------------------------------
255 * Init C runtime environment:
256 * - Zero-initialise the NOBITS sections. There are 2 of them:
257 * - the .bss section;
258 * - the coherent memory section (if any).
259 * - Relocate the data section from ROM to RAM, if required.
260 * ---------------------------------------------------------------------
261 */
262 .if \_init_c_runtime
Masahiro Yamada441bfdd2016-12-25 23:36:24 +0900263#ifdef IMAGE_BL32
Yatharth Kocharf528faf2016-06-28 16:58:26 +0100264 /* -----------------------------------------------------------------
265 * Invalidate the RW memory used by the BL32 (SP_MIN) image. This
266 * includes the data and NOBITS sections. This is done to
267 * safeguard against possible corruption of this memory by
268 * dirty cache lines in a system cache as a result of use by
269 * an earlier boot loader stage.
270 * -----------------------------------------------------------------
271 */
272 ldr r0, =__RW_START__
273 ldr r1, =__RW_END__
274 sub r1, r1, r0
275 bl inv_dcache_range
276#endif /* IMAGE_BL32 */
277
278 ldr r0, =__BSS_START__
279 ldr r1, =__BSS_SIZE__
280 bl zeromem
281
282#if USE_COHERENT_MEM
283 ldr r0, =__COHERENT_RAM_START__
284 ldr r1, =__COHERENT_RAM_UNALIGNED_SIZE__
285 bl zeromem
286#endif
287
Masahiro Yamada441bfdd2016-12-25 23:36:24 +0900288#ifdef IMAGE_BL1
Yatharth Kocharf528faf2016-06-28 16:58:26 +0100289 /* -----------------------------------------------------
290 * Copy data from ROM to RAM.
291 * -----------------------------------------------------
292 */
293 ldr r0, =__DATA_RAM_START__
294 ldr r1, =__DATA_ROM_START__
295 ldr r2, =__DATA_SIZE__
Yatharth Kocharc44c5af2016-09-28 11:00:05 +0100296 bl memcpy4
Yatharth Kocharf528faf2016-06-28 16:58:26 +0100297#endif
298 .endif /* _init_c_runtime */
299
300 /* ---------------------------------------------------------------------
301 * Allocate a stack whose memory will be marked as Normal-IS-WBWA when
302 * the MMU is enabled. There is no risk of reading stale stack memory
303 * after enabling the MMU as only the primary CPU is running at the
304 * moment.
305 * ---------------------------------------------------------------------
306 */
307 bl plat_set_my_stack
Douglas Raillard306593d2017-02-24 18:14:15 +0000308
309#if STACK_PROTECTOR_ENABLED
310 .if \_init_c_runtime
311 bl update_stack_protector_canary
312 .endif /* _init_c_runtime */
313#endif
Yatharth Kocharf528faf2016-06-28 16:58:26 +0100314 .endm
315
316#endif /* __EL3_COMMON_MACROS_S__ */