Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 1 | /* |
Steven Kao | 4d160ac | 2016-12-23 16:05:13 +0800 | [diff] [blame] | 2 | * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef __TEGRA_DEF_H__ |
| 8 | #define __TEGRA_DEF_H__ |
| 9 | |
Varun Wadekar | 761ca73 | 2017-04-24 14:17:12 -0700 | [diff] [blame] | 10 | #include <utils_def.h> |
| 11 | |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 12 | /******************************************************************************* |
| 13 | * This value is used by the PSCI implementation during the `SYSTEM_SUSPEND` |
| 14 | * call as the `state-id` field in the 'power state' parameter. |
| 15 | ******************************************************************************/ |
Varun Wadekar | 761ca73 | 2017-04-24 14:17:12 -0700 | [diff] [blame] | 16 | #define PSTATE_ID_SOC_POWERDN U(0xD) |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 17 | |
| 18 | /******************************************************************************* |
Varun Wadekar | 3ce5499 | 2016-01-19 13:55:19 -0800 | [diff] [blame] | 19 | * Platform power states (used by PSCI framework) |
| 20 | * |
| 21 | * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID |
| 22 | * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID |
| 23 | ******************************************************************************/ |
Varun Wadekar | 761ca73 | 2017-04-24 14:17:12 -0700 | [diff] [blame] | 24 | #define PLAT_MAX_RET_STATE U(1) |
| 25 | #define PLAT_MAX_OFF_STATE (PSTATE_ID_SOC_POWERDN + U(1)) |
Varun Wadekar | 3ce5499 | 2016-01-19 13:55:19 -0800 | [diff] [blame] | 26 | |
| 27 | /******************************************************************************* |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 28 | * GIC memory map |
| 29 | ******************************************************************************/ |
Varun Wadekar | 761ca73 | 2017-04-24 14:17:12 -0700 | [diff] [blame] | 30 | #define TEGRA_GICD_BASE U(0x50041000) |
| 31 | #define TEGRA_GICC_BASE U(0x50042000) |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 32 | |
| 33 | /******************************************************************************* |
| 34 | * Tegra micro-seconds timer constants |
| 35 | ******************************************************************************/ |
Varun Wadekar | 761ca73 | 2017-04-24 14:17:12 -0700 | [diff] [blame] | 36 | #define TEGRA_TMRUS_BASE U(0x60005010) |
| 37 | #define TEGRA_TMRUS_SIZE U(0x1000) |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 38 | |
| 39 | /******************************************************************************* |
| 40 | * Tegra Clock and Reset Controller constants |
| 41 | ******************************************************************************/ |
Varun Wadekar | 761ca73 | 2017-04-24 14:17:12 -0700 | [diff] [blame] | 42 | #define TEGRA_CAR_RESET_BASE U(0x60006000) |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 43 | |
| 44 | /******************************************************************************* |
| 45 | * Tegra Flow Controller constants |
| 46 | ******************************************************************************/ |
Varun Wadekar | 761ca73 | 2017-04-24 14:17:12 -0700 | [diff] [blame] | 47 | #define TEGRA_FLOWCTRL_BASE U(0x60007000) |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 48 | |
| 49 | /******************************************************************************* |
| 50 | * Tegra Secure Boot Controller constants |
| 51 | ******************************************************************************/ |
Varun Wadekar | 761ca73 | 2017-04-24 14:17:12 -0700 | [diff] [blame] | 52 | #define TEGRA_SB_BASE U(0x6000C200) |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 53 | |
| 54 | /******************************************************************************* |
| 55 | * Tegra Exception Vectors constants |
| 56 | ******************************************************************************/ |
Varun Wadekar | 761ca73 | 2017-04-24 14:17:12 -0700 | [diff] [blame] | 57 | #define TEGRA_EVP_BASE U(0x6000F000) |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 58 | |
| 59 | /******************************************************************************* |
Varun Wadekar | 28dcc21 | 2016-07-20 10:28:51 -0700 | [diff] [blame] | 60 | * Tegra Miscellaneous register constants |
| 61 | ******************************************************************************/ |
Varun Wadekar | 761ca73 | 2017-04-24 14:17:12 -0700 | [diff] [blame] | 62 | #define TEGRA_MISC_BASE U(0x70000000) |
| 63 | #define HARDWARE_REVISION_OFFSET U(0x804) |
Varun Wadekar | 28dcc21 | 2016-07-20 10:28:51 -0700 | [diff] [blame] | 64 | |
| 65 | /******************************************************************************* |
Varun Wadekar | d2014c6 | 2015-10-29 10:37:28 +0530 | [diff] [blame] | 66 | * Tegra UART controller base addresses |
| 67 | ******************************************************************************/ |
Varun Wadekar | 761ca73 | 2017-04-24 14:17:12 -0700 | [diff] [blame] | 68 | #define TEGRA_UARTA_BASE U(0x70006000) |
| 69 | #define TEGRA_UARTB_BASE U(0x70006040) |
| 70 | #define TEGRA_UARTC_BASE U(0x70006200) |
| 71 | #define TEGRA_UARTD_BASE U(0x70006300) |
| 72 | #define TEGRA_UARTE_BASE U(0x70006400) |
Varun Wadekar | d2014c6 | 2015-10-29 10:37:28 +0530 | [diff] [blame] | 73 | |
| 74 | /******************************************************************************* |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 75 | * Tegra Power Mgmt Controller constants |
| 76 | ******************************************************************************/ |
Varun Wadekar | 761ca73 | 2017-04-24 14:17:12 -0700 | [diff] [blame] | 77 | #define TEGRA_PMC_BASE U(0x7000E400) |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 78 | |
| 79 | /******************************************************************************* |
| 80 | * Tegra Memory Controller constants |
| 81 | ******************************************************************************/ |
Varun Wadekar | 761ca73 | 2017-04-24 14:17:12 -0700 | [diff] [blame] | 82 | #define TEGRA_MC_BASE U(0x70019000) |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 83 | |
Varun Wadekar | 64443ca | 2016-12-12 16:14:57 -0800 | [diff] [blame] | 84 | /* TZDRAM carveout configuration registers */ |
Varun Wadekar | 761ca73 | 2017-04-24 14:17:12 -0700 | [diff] [blame] | 85 | #define MC_SECURITY_CFG0_0 U(0x70) |
| 86 | #define MC_SECURITY_CFG1_0 U(0x74) |
| 87 | #define MC_SECURITY_CFG3_0 U(0x9BC) |
Varun Wadekar | 64443ca | 2016-12-12 16:14:57 -0800 | [diff] [blame] | 88 | |
| 89 | /* Video Memory carveout configuration registers */ |
Varun Wadekar | 761ca73 | 2017-04-24 14:17:12 -0700 | [diff] [blame] | 90 | #define MC_VIDEO_PROTECT_BASE_HI U(0x978) |
| 91 | #define MC_VIDEO_PROTECT_BASE_LO U(0x648) |
| 92 | #define MC_VIDEO_PROTECT_SIZE_MB U(0x64c) |
Varun Wadekar | 64443ca | 2016-12-12 16:14:57 -0800 | [diff] [blame] | 93 | |
Varun Wadekar | 0dc9181 | 2015-12-30 15:06:41 -0800 | [diff] [blame] | 94 | /******************************************************************************* |
| 95 | * Tegra TZRAM constants |
| 96 | ******************************************************************************/ |
Varun Wadekar | 761ca73 | 2017-04-24 14:17:12 -0700 | [diff] [blame] | 97 | #define TEGRA_TZRAM_BASE U(0x7C010000) |
| 98 | #define TEGRA_TZRAM_SIZE U(0x10000) |
Varun Wadekar | 0dc9181 | 2015-12-30 15:06:41 -0800 | [diff] [blame] | 99 | |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 100 | #endif /* __TEGRA_DEF_H__ */ |