Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 1 | /* |
Antonio Nino Diaz | 7a4ff68 | 2017-03-28 13:56:21 +0100 | [diff] [blame] | 2 | * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. |
Varun Wadekar | b5b15b2 | 2018-05-17 10:10:25 -0700 | [diff] [blame^] | 3 | * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 4 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 5 | * SPDX-License-Identifier: BSD-3-Clause |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 6 | */ |
| 7 | |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 8 | #include <assert.h> |
| 9 | |
| 10 | #include <platform_def.h> |
| 11 | |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 12 | #include <arch.h> |
| 13 | #include <arch_helpers.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 14 | #include <common/debug.h> |
| 15 | #include <drivers/delay_timer.h> |
Isla Mitchell | e363146 | 2017-07-14 10:46:32 +0100 | [diff] [blame] | 16 | #include <denver.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 17 | #include <lib/mmio.h> |
| 18 | #include <lib/psci/psci.h> |
| 19 | |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 20 | #include <flowctrl.h> |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 21 | #include <pmc.h> |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 22 | #include <tegra_def.h> |
| 23 | #include <tegra_private.h> |
| 24 | |
| 25 | /* |
| 26 | * Register used to clear CPU reset signals. Each CPU has two reset |
| 27 | * signals: CPU reset (3:0) and Core reset (19:16) |
| 28 | */ |
| 29 | #define CPU_CMPLX_RESET_CLR 0x344 |
| 30 | #define CPU_CORE_RESET_MASK 0x10001 |
| 31 | |
Varun Wadekar | 8b82fae | 2015-11-09 17:39:28 -0800 | [diff] [blame] | 32 | /* Clock and Reset controller registers for system clock's settings */ |
| 33 | #define SCLK_RATE 0x30 |
| 34 | #define SCLK_BURST_POLICY 0x28 |
| 35 | #define SCLK_BURST_POLICY_DEFAULT 0x10000000 |
| 36 | |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 37 | static int cpu_powergate_mask[PLATFORM_MAX_CPUS_PER_CLUSTER]; |
| 38 | |
Varun Wadekar | b5b15b2 | 2018-05-17 10:10:25 -0700 | [diff] [blame^] | 39 | plat_local_state_t tegra_soc_get_target_pwr_state(uint32_t lvl, |
| 40 | const plat_local_state_t *states, |
| 41 | uint32_t ncpu) |
| 42 | { |
| 43 | plat_local_state_t target = PLAT_MAX_OFF_STATE, temp; |
| 44 | uint32_t num_cpu = ncpu; |
| 45 | const plat_local_state_t *local_state = states; |
| 46 | |
| 47 | (void)lvl; |
| 48 | |
| 49 | assert(ncpu != 0U); |
| 50 | |
| 51 | do { |
| 52 | temp = *local_state; |
| 53 | if ((temp < target)) { |
| 54 | target = temp; |
| 55 | } |
| 56 | --num_cpu; |
| 57 | local_state++; |
| 58 | } while (num_cpu != 0U); |
| 59 | |
| 60 | return target; |
| 61 | } |
| 62 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 63 | int32_t tegra_soc_validate_power_state(unsigned int power_state, |
| 64 | psci_power_state_t *req_state) |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 65 | { |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 66 | int state_id = psci_get_pstate_id(power_state); |
| 67 | int cpu = read_mpidr() & MPIDR_CPU_MASK; |
| 68 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 69 | /* |
| 70 | * Sanity check the requested state id, power level and CPU number. |
| 71 | * Currently T132 only supports SYSTEM_SUSPEND on last standing CPU |
| 72 | * i.e. CPU 0 |
| 73 | */ |
Varun Wadekar | 6077dce | 2016-01-27 11:31:06 -0800 | [diff] [blame] | 74 | if ((state_id != PSTATE_ID_SOC_POWERDN) || (cpu != 0)) { |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 75 | ERROR("unsupported state id @ power level\n"); |
| 76 | return PSCI_E_INVALID_PARAMS; |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 77 | } |
| 78 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 79 | /* Set lower power states to PLAT_MAX_OFF_STATE */ |
Varun Wadekar | 66231d1 | 2017-06-07 09:57:42 -0700 | [diff] [blame] | 80 | for (uint32_t i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++) |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 81 | req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; |
| 82 | |
| 83 | /* Set the SYSTEM_SUSPEND state-id */ |
| 84 | req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] = |
| 85 | PSTATE_ID_SOC_POWERDN; |
| 86 | |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 87 | return PSCI_E_SUCCESS; |
| 88 | } |
| 89 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 90 | int tegra_soc_pwr_domain_on(u_register_t mpidr) |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 91 | { |
| 92 | int cpu = mpidr & MPIDR_CPU_MASK; |
| 93 | uint32_t mask = CPU_CORE_RESET_MASK << cpu; |
| 94 | |
| 95 | if (cpu_powergate_mask[cpu] == 0) { |
| 96 | |
| 97 | /* Deassert CPU reset signals */ |
| 98 | mmio_write_32(TEGRA_CAR_RESET_BASE + CPU_CMPLX_RESET_CLR, mask); |
| 99 | |
| 100 | /* Power on CPU using PMC */ |
| 101 | tegra_pmc_cpu_on(cpu); |
| 102 | |
| 103 | /* Fill in the CPU powergate mask */ |
| 104 | cpu_powergate_mask[cpu] = 1; |
| 105 | |
| 106 | } else { |
| 107 | /* Power on CPU using Flow Controller */ |
| 108 | tegra_fc_cpu_on(cpu); |
| 109 | } |
| 110 | |
| 111 | return PSCI_E_SUCCESS; |
| 112 | } |
| 113 | |
Varun Wadekar | 6eec6d6 | 2016-03-03 13:28:10 -0800 | [diff] [blame] | 114 | int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) |
| 115 | { |
| 116 | /* |
| 117 | * Lock scratch registers which hold the CPU vectors |
| 118 | */ |
| 119 | tegra_pmc_lock_cpu_vectors(); |
| 120 | |
| 121 | return PSCI_E_SUCCESS; |
| 122 | } |
| 123 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 124 | int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state) |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 125 | { |
Steven Kao | d417cea | 2017-06-14 14:02:23 +0800 | [diff] [blame] | 126 | uint64_t val; |
| 127 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 128 | tegra_fc_cpu_off(read_mpidr() & MPIDR_CPU_MASK); |
Varun Wadekar | d43583c | 2016-02-22 11:09:41 -0800 | [diff] [blame] | 129 | |
| 130 | /* Disable DCO operations */ |
| 131 | denver_disable_dco(); |
| 132 | |
| 133 | /* Power down the CPU */ |
Steven Kao | d417cea | 2017-06-14 14:02:23 +0800 | [diff] [blame] | 134 | val = read_actlr_el1() & ~ACTLR_EL1_PMSTATE_MASK; |
| 135 | write_actlr_el1(val | DENVER_CPU_STATE_POWER_DOWN); |
Varun Wadekar | d43583c | 2016-02-22 11:09:41 -0800 | [diff] [blame] | 136 | |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 137 | return PSCI_E_SUCCESS; |
| 138 | } |
| 139 | |
Varun Wadekar | b5b15b2 | 2018-05-17 10:10:25 -0700 | [diff] [blame^] | 140 | int32_t tegra_soc_cpu_standby(plat_local_state_t cpu_state) |
| 141 | { |
| 142 | (void)cpu_state; |
| 143 | return PSCI_E_SUCCESS; |
| 144 | } |
| 145 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 146 | int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 147 | { |
Steven Kao | d417cea | 2017-06-14 14:02:23 +0800 | [diff] [blame] | 148 | uint64_t val; |
| 149 | |
Antonio Nino Diaz | 7a4ff68 | 2017-03-28 13:56:21 +0100 | [diff] [blame] | 150 | #if ENABLE_ASSERTIONS |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 151 | int cpu = read_mpidr() & MPIDR_CPU_MASK; |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 152 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 153 | /* SYSTEM_SUSPEND only on CPU0 */ |
| 154 | assert(cpu == 0); |
| 155 | #endif |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 156 | |
| 157 | /* Allow restarting CPU #1 using PMC on suspend exit */ |
| 158 | cpu_powergate_mask[1] = 0; |
| 159 | |
| 160 | /* Program FC to enter suspend state */ |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 161 | tegra_fc_cpu_powerdn(read_mpidr()); |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 162 | |
Varun Wadekar | d43583c | 2016-02-22 11:09:41 -0800 | [diff] [blame] | 163 | /* Disable DCO operations */ |
| 164 | denver_disable_dco(); |
| 165 | |
| 166 | /* Program the suspend state ID */ |
Steven Kao | d417cea | 2017-06-14 14:02:23 +0800 | [diff] [blame] | 167 | val = read_actlr_el1() & ~ACTLR_EL1_PMSTATE_MASK; |
| 168 | write_actlr_el1(val | target_state->pwr_domain_state[PLAT_MAX_PWR_LVL]); |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 169 | |
| 170 | return PSCI_E_SUCCESS; |
| 171 | } |
Varun Wadekar | 8b82fae | 2015-11-09 17:39:28 -0800 | [diff] [blame] | 172 | |
Varun Wadekar | b5b15b2 | 2018-05-17 10:10:25 -0700 | [diff] [blame^] | 173 | int32_t tegra_soc_pwr_domain_suspend_pwrdown_early(const psci_power_state_t *target_state) |
| 174 | { |
| 175 | return PSCI_E_NOT_SUPPORTED; |
| 176 | } |
| 177 | |
| 178 | int tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state) |
| 179 | { |
| 180 | return PSCI_E_SUCCESS; |
| 181 | } |
| 182 | |
Varun Wadekar | 8b82fae | 2015-11-09 17:39:28 -0800 | [diff] [blame] | 183 | int tegra_soc_prepare_system_reset(void) |
| 184 | { |
| 185 | /* |
| 186 | * Set System Clock (SCLK) to POR default so that the clock source |
| 187 | * for the PMC APB clock would not be changed due to system reset. |
| 188 | */ |
| 189 | mmio_write_32((uintptr_t)TEGRA_CAR_RESET_BASE + SCLK_BURST_POLICY, |
| 190 | SCLK_BURST_POLICY_DEFAULT); |
| 191 | mmio_write_32((uintptr_t)TEGRA_CAR_RESET_BASE + SCLK_RATE, 0); |
| 192 | |
| 193 | /* Wait 1 ms to make sure clock source/device logic is stabilized. */ |
| 194 | mdelay(1); |
| 195 | |
| 196 | return PSCI_E_SUCCESS; |
| 197 | } |
Varun Wadekar | b5b15b2 | 2018-05-17 10:10:25 -0700 | [diff] [blame^] | 198 | |
| 199 | __dead2 void tegra_soc_prepare_system_off(void) |
| 200 | { |
| 201 | ERROR("Tegra System Off: operation not handled.\n"); |
| 202 | panic(); |
| 203 | } |