blob: ddc750243b70eba612adf49e8a6733ac71d6e7a7 [file] [log] [blame]
developerc0c07822021-03-29 16:50:30 +08001/*
2 * Copyright (c) 2020, MediaTek Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <common/debug.h>
8#include <common/runtime_svc.h>
Rex-BC Chenb48c6c42021-04-12 11:10:31 +08009#include <mt_dp.h>
developer0d3844d2021-07-09 16:55:51 +080010#include <mt_spm.h>
11#include <mt_spm_vcorefs.h>
Rex-BC Chenb48c6c42021-04-12 11:10:31 +080012#include <mtk_sip_svc.h>
Rex-BC Chen17903042021-08-10 11:10:58 +080013#include <plat_dfd.h>
Rex-BC Chenb48c6c42021-04-12 11:10:31 +080014#include "plat_sip_calls.h"
developerc0c07822021-03-29 16:50:30 +080015
16uintptr_t mediatek_plat_sip_handler(uint32_t smc_fid,
17 u_register_t x1,
18 u_register_t x2,
19 u_register_t x3,
20 u_register_t x4,
21 void *cookie,
22 void *handle,
23 u_register_t flags)
24{
Rex-BC Chenb48c6c42021-04-12 11:10:31 +080025 int32_t ret;
26 uint32_t ret_val;
27
developerc0c07822021-03-29 16:50:30 +080028 switch (smc_fid) {
Rex-BC Chenb48c6c42021-04-12 11:10:31 +080029 case MTK_SIP_DP_CONTROL_AARCH32:
30 case MTK_SIP_DP_CONTROL_AARCH64:
31 ret = dp_secure_handler(x1, x2, &ret_val);
32 SMC_RET2(handle, ret, ret_val);
33 break;
developer0d3844d2021-07-09 16:55:51 +080034 case MTK_SIP_VCORE_CONTROL_ARCH32:
35 case MTK_SIP_VCORE_CONTROL_ARCH64:
36 ret = spm_vcorefs_v2_args(x1, x2, x3, &x4);
37 SMC_RET2(handle, ret, x4);
38 break;
Rex-BC Chen17903042021-08-10 11:10:58 +080039 case MTK_SIP_KERNEL_DFD_AARCH32:
40 case MTK_SIP_KERNEL_DFD_AARCH64:
41 ret = dfd_smc_dispatcher(x1, x2, x3, x4);
42 SMC_RET1(handle, ret);
43 break;
developerc0c07822021-03-29 16:50:30 +080044 default:
45 ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
46 break;
47 }
48
49 SMC_RET1(handle, SMC_UNK);
50}