blob: ee36898ca83e7be5449e0d5512396330895b2e5c [file] [log] [blame]
developerc0c07822021-03-29 16:50:30 +08001/*
2 * Copyright (c) 2020, MediaTek Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <common/debug.h>
8#include <common/runtime_svc.h>
Rex-BC Chenb48c6c42021-04-12 11:10:31 +08009#include <mt_dp.h>
developer0d3844d2021-07-09 16:55:51 +080010#include <mt_spm.h>
11#include <mt_spm_vcorefs.h>
Rex-BC Chenb48c6c42021-04-12 11:10:31 +080012#include <mtk_sip_svc.h>
13#include "plat_sip_calls.h"
developerc0c07822021-03-29 16:50:30 +080014
15uintptr_t mediatek_plat_sip_handler(uint32_t smc_fid,
16 u_register_t x1,
17 u_register_t x2,
18 u_register_t x3,
19 u_register_t x4,
20 void *cookie,
21 void *handle,
22 u_register_t flags)
23{
Rex-BC Chenb48c6c42021-04-12 11:10:31 +080024 int32_t ret;
25 uint32_t ret_val;
26
developerc0c07822021-03-29 16:50:30 +080027 switch (smc_fid) {
Rex-BC Chenb48c6c42021-04-12 11:10:31 +080028 case MTK_SIP_DP_CONTROL_AARCH32:
29 case MTK_SIP_DP_CONTROL_AARCH64:
30 ret = dp_secure_handler(x1, x2, &ret_val);
31 SMC_RET2(handle, ret, ret_val);
32 break;
developer0d3844d2021-07-09 16:55:51 +080033 case MTK_SIP_VCORE_CONTROL_ARCH32:
34 case MTK_SIP_VCORE_CONTROL_ARCH64:
35 ret = spm_vcorefs_v2_args(x1, x2, x3, &x4);
36 SMC_RET2(handle, ret, x4);
37 break;
developerc0c07822021-03-29 16:50:30 +080038 default:
39 ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
40 break;
41 }
42
43 SMC_RET1(handle, SMC_UNK);
44}