| Joel Hutton | 9463cae | 2018-05-04 15:09:47 +0100 | [diff] [blame] | 1 | /* |
| johpow01 | eb14610 | 2021-05-03 13:37:13 -0500 | [diff] [blame] | 2 | * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved. |
| Joel Hutton | 9463cae | 2018-05-04 15:09:47 +0100 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| Balint Dobszay | cc94264 | 2019-07-03 13:02:56 +0200 | [diff] [blame] | 7 | #ifndef CORTEX_A77_H |
| 8 | #define CORTEX_A77_H |
| Joel Hutton | 9463cae | 2018-05-04 15:09:47 +0100 | [diff] [blame] | 9 | |
| Antonio Nino Diaz | 5e79cfe | 2019-02-11 13:34:15 +0000 | [diff] [blame] | 10 | #include <lib/utils_def.h> |
| 11 | |
| Balint Dobszay | cc94264 | 2019-07-03 13:02:56 +0200 | [diff] [blame] | 12 | /* Cortex-A77 MIDR */ |
| 13 | #define CORTEX_A77_MIDR U(0x410FD0D0) |
| Joel Hutton | 9463cae | 2018-05-04 15:09:47 +0100 | [diff] [blame] | 14 | |
| 15 | /******************************************************************************* |
| 16 | * CPU Extended Control register specific definitions. |
| 17 | ******************************************************************************/ |
| Balint Dobszay | cc94264 | 2019-07-03 13:02:56 +0200 | [diff] [blame] | 18 | #define CORTEX_A77_CPUECTLR_EL1 S3_0_C15_C1_4 |
| johpow01 | a2fa12c | 2020-09-10 13:39:26 -0500 | [diff] [blame] | 19 | #define CORTEX_A77_CPUECTLR_EL1_BIT_8 (ULL(1) << 8) |
| Joel Hutton | 9463cae | 2018-05-04 15:09:47 +0100 | [diff] [blame] | 20 | |
| 21 | /******************************************************************************* |
| 22 | * CPU Power Control register specific definitions. |
| 23 | ******************************************************************************/ |
| Balint Dobszay | cc94264 | 2019-07-03 13:02:56 +0200 | [diff] [blame] | 24 | #define CORTEX_A77_CPUPWRCTLR_EL1 S3_0_C15_C2_7 |
| 25 | #define CORTEX_A77_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0) |
| Joel Hutton | 9463cae | 2018-05-04 15:09:47 +0100 | [diff] [blame] | 26 | |
| johpow01 | eb14610 | 2021-05-03 13:37:13 -0500 | [diff] [blame] | 27 | /******************************************************************************* |
| 28 | * CPU Auxiliary Control register specific definitions. |
| 29 | ******************************************************************************/ |
| 30 | #define CORTEX_A77_ACTLR2_EL1 S3_0_C15_C1_1 |
| 31 | #define CORTEX_A77_ACTLR2_EL1_BIT_2 (ULL(1) << 2) |
| 32 | |
| laurenw-arm | 99ad976 | 2020-07-14 14:18:34 -0500 | [diff] [blame] | 33 | #define CORTEX_A77_CPUPSELR_EL3 S3_6_C15_C8_0 |
| 34 | #define CORTEX_A77_CPUPCR_EL3 S3_6_C15_C8_1 |
| 35 | #define CORTEX_A77_CPUPOR_EL3 S3_6_C15_C8_2 |
| 36 | #define CORTEX_A77_CPUPMR_EL3 S3_6_C15_C8_3 |
| 37 | #define CORTEX_A77_CPUPOR2_EL3 S3_6_C15_C8_4 |
| 38 | #define CORTEX_A77_CPUPMR2_EL3 S3_6_C15_C8_5 |
| 39 | |
| Balint Dobszay | cc94264 | 2019-07-03 13:02:56 +0200 | [diff] [blame] | 40 | #endif /* CORTEX_A77_H */ |