blob: 6ea0b155895b0fa6af25e9c99a7dbe428bcfe8d3 [file] [log] [blame]
Sandrine Bailleux798140d2014-07-17 16:06:39 +01001/*
2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <arch_helpers.h>
Juan Castillob3286c02014-10-20 12:29:58 +010032#include <arm_gic.h>
Sandrine Bailleux798140d2014-07-17 16:06:39 +010033#include <assert.h>
34#include <bl_common.h>
35#include <debug.h>
36#include <mmio.h>
37#include <platform.h>
38#include <platform_def.h>
39#include <xlat_tables.h>
40#include "../juno_def.h"
41
Soby Mathewb08bc042014-09-03 17:48:44 +010042#define MAP_MHU_SECURE MAP_REGION_FLAT(MHU_SECURE_BASE, \
43 MHU_SECURE_SIZE, \
44 (MHU_PAYLOAD_CACHED ? \
45 MT_MEMORY : MT_DEVICE) \
46 | MT_RW | MT_SECURE)
47
48#define MAP_FLASH MAP_REGION_FLAT(FLASH_BASE, \
49 FLASH_SIZE, \
50 MT_MEMORY | MT_RO | MT_SECURE)
51
52#define MAP_IOFPGA MAP_REGION_FLAT(IOFPGA_BASE, \
53 IOFPGA_SIZE, \
54 MT_DEVICE | MT_RW | MT_SECURE)
55
56#define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \
57 DEVICE0_SIZE, \
58 MT_DEVICE | MT_RW | MT_SECURE)
59
60#define MAP_DEVICE1 MAP_REGION_FLAT(DEVICE1_BASE, \
61 DEVICE1_SIZE, \
62 MT_DEVICE | MT_RW | MT_SECURE)
63
Juan Castillo921b8772014-09-05 17:29:38 +010064#define MAP_NS_DRAM MAP_REGION_FLAT(DRAM_NS_BASE, \
65 DRAM_NS_SIZE, \
Soby Mathewb08bc042014-09-03 17:48:44 +010066 MT_MEMORY | MT_RW | MT_NS)
Juan Castillo921b8772014-09-05 17:29:38 +010067
68#define MAP_TSP_MEM MAP_REGION_FLAT(TSP_SEC_MEM_BASE, \
69 TSP_SEC_MEM_SIZE, \
70 MT_MEMORY | MT_RW | MT_SECURE)
71
Sandrine Bailleux798140d2014-07-17 16:06:39 +010072/*
Soby Mathewb08bc042014-09-03 17:48:44 +010073 * Table of regions for different BL stages to map using the MMU.
Sandrine Bailleux798140d2014-07-17 16:06:39 +010074 * This doesn't include Trusted RAM as the 'mem_layout' argument passed to
75 * configure_mmu_elx() will give the available subset of that,
76 */
Soby Mathewb08bc042014-09-03 17:48:44 +010077#if IMAGE_BL1
Sandrine Bailleux798140d2014-07-17 16:06:39 +010078static const mmap_region_t juno_mmap[] = {
Soby Mathewb08bc042014-09-03 17:48:44 +010079 MAP_MHU_SECURE,
80 MAP_FLASH,
81 MAP_IOFPGA,
82 MAP_DEVICE0,
83 MAP_DEVICE1,
Sandrine Bailleux798140d2014-07-17 16:06:39 +010084 {0}
85};
Soby Mathewb08bc042014-09-03 17:48:44 +010086#endif
87#if IMAGE_BL2
88static const mmap_region_t juno_mmap[] = {
89 MAP_MHU_SECURE,
90 MAP_FLASH,
91 MAP_IOFPGA,
92 MAP_DEVICE0,
93 MAP_DEVICE1,
Juan Castillo921b8772014-09-05 17:29:38 +010094 MAP_NS_DRAM,
95 MAP_TSP_MEM,
Soby Mathewb08bc042014-09-03 17:48:44 +010096 {0}
97};
98#endif
99#if IMAGE_BL31
100static const mmap_region_t juno_mmap[] = {
101 MAP_MHU_SECURE,
102 MAP_IOFPGA,
103 MAP_DEVICE0,
104 MAP_DEVICE1,
105 {0}
106};
107#endif
108#if IMAGE_BL32
109static const mmap_region_t juno_mmap[] = {
110 MAP_IOFPGA,
111 MAP_DEVICE0,
112 MAP_DEVICE1,
113 {0}
114};
115#endif
Sandrine Bailleux798140d2014-07-17 16:06:39 +0100116
Soby Mathew13ee9682015-01-22 11:22:22 +0000117CASSERT((sizeof(juno_mmap)/sizeof(juno_mmap[0])) + JUNO_BL_REGIONS \
118 <= MAX_MMAP_REGIONS, assert_max_mmap_regions);
119
Juan Castillob3286c02014-10-20 12:29:58 +0100120/* Array of secure interrupts to be configured by the gic driver */
121const unsigned int irq_sec_array[] = {
122 IRQ_MHU,
123 IRQ_GPU_SMMU_0,
124 IRQ_GPU_SMMU_1,
125 IRQ_ETR_SMMU,
126 IRQ_TZC400,
127 IRQ_TZ_WDOG,
128 IRQ_SEC_PHY_TIMER,
129 IRQ_SEC_SGI_0,
130 IRQ_SEC_SGI_1,
131 IRQ_SEC_SGI_2,
132 IRQ_SEC_SGI_3,
133 IRQ_SEC_SGI_4,
134 IRQ_SEC_SGI_5,
135 IRQ_SEC_SGI_6,
136 IRQ_SEC_SGI_7
137};
138
139const unsigned int num_sec_irqs = sizeof(irq_sec_array) /
140 sizeof(irq_sec_array[0]);
141
Sandrine Bailleux798140d2014-07-17 16:06:39 +0100142/*******************************************************************************
143 * Macro generating the code for the function setting up the pagetables as per
144 * the platform memory map & initialize the mmu, for the given exception level
145 ******************************************************************************/
Soby Mathew2ae20432015-01-08 18:02:44 +0000146#if USE_COHERENT_MEM
Sandrine Bailleux798140d2014-07-17 16:06:39 +0100147#define DEFINE_CONFIGURE_MMU_EL(_el) \
148 void configure_mmu_el##_el(unsigned long total_base, \
149 unsigned long total_size, \
150 unsigned long ro_start, \
151 unsigned long ro_limit, \
152 unsigned long coh_start, \
153 unsigned long coh_limit) \
154 { \
155 mmap_add_region(total_base, total_base, \
156 total_size, \
157 MT_MEMORY | MT_RW | MT_SECURE); \
158 mmap_add_region(ro_start, ro_start, \
159 ro_limit - ro_start, \
160 MT_MEMORY | MT_RO | MT_SECURE); \
161 mmap_add_region(coh_start, coh_start, \
162 coh_limit - coh_start, \
163 MT_DEVICE | MT_RW | MT_SECURE); \
164 mmap_add(juno_mmap); \
165 init_xlat_tables(); \
166 \
167 enable_mmu_el##_el(0); \
168 }
Soby Mathew2ae20432015-01-08 18:02:44 +0000169#else
170#define DEFINE_CONFIGURE_MMU_EL(_el) \
171 void configure_mmu_el##_el(unsigned long total_base, \
172 unsigned long total_size, \
173 unsigned long ro_start, \
174 unsigned long ro_limit) \
175 { \
176 mmap_add_region(total_base, total_base, \
177 total_size, \
178 MT_MEMORY | MT_RW | MT_SECURE); \
179 mmap_add_region(ro_start, ro_start, \
180 ro_limit - ro_start, \
181 MT_MEMORY | MT_RO | MT_SECURE); \
182 mmap_add(juno_mmap); \
183 init_xlat_tables(); \
184 \
185 enable_mmu_el##_el(0); \
186 }
187#endif
Sandrine Bailleux798140d2014-07-17 16:06:39 +0100188/* Define EL1 and EL3 variants of the function initialising the MMU */
189DEFINE_CONFIGURE_MMU_EL(1)
190DEFINE_CONFIGURE_MMU_EL(3)
191
192
193unsigned long plat_get_ns_image_entrypoint(void)
194{
195 return NS_IMAGE_OFFSET;
196}
197
198uint64_t plat_get_syscnt_freq(void)
199{
200 uint64_t counter_base_frequency;
201
202 /* Read the frequency from Frequency modes table */
203 counter_base_frequency = mmio_read_32(SYS_CNTCTL_BASE + CNTFID_OFF);
204
205 /* The first entry of the frequency modes table must not be 0 */
206 if (counter_base_frequency == 0)
207 panic();
208
209 return counter_base_frequency;
210}
Juan Castillob3286c02014-10-20 12:29:58 +0100211
212void plat_gic_init(void)
213{
214 arm_gic_init(GICC_BASE, GICD_BASE, 0, irq_sec_array, num_sec_irqs);
215}