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git01.mediatek.com / filogic / atf / b48c6c4a562ace1aad0dc1b444a64a24d73e84dd / . / plat / arm / board / rde1edge / platform.mk
blob: 0f9dd496a74018b814579933efb3e9cdb696a253 [file] [log] [blame]
Chandni Cherukuri626a52d2018-08-16 13:43:23 +0530[diff] [blame]1#
Vijayenthiran Subramaniamf5cb00f2019-12-27 19:27:57 +0530[diff] [blame]2# Copyright (c) 2018-2020, Arm Limited. All rights reserved.
Chandni Cherukuri626a52d2018-08-16 13:43:23 +0530[diff] [blame]3#
4# SPDX-License-Identifier: BSD-3-Clause
5#
6
7include plat/arm/css/sgi/sgi-common.mk
8
Chandni Cherukuri533b5542019-02-22 16:44:49 +0530[diff] [blame]9RDE1EDGE_BASE = plat/arm/board/rde1edge
Chandni Cherukuri626a52d2018-08-16 13:43:23 +0530[diff] [blame]10
Chandni Cherukuri533b5542019-02-22 16:44:49 +0530[diff] [blame]11PLAT_INCLUDES += -I${RDE1EDGE_BASE}/include/
Chandni Cherukuri626a52d2018-08-16 13:43:23 +0530[diff] [blame]12
John Tsichritzis16e6d9f2019-02-19 14:01:55 +0000[diff] [blame]13SGI_CPU_SOURCES := lib/cpus/aarch64/neoverse_e1.S
Chandni Cherukuri626a52d2018-08-16 13:43:23 +0530[diff] [blame]14
Aditya Angadi502d0ac2020-11-18 08:27:15 +0530[diff] [blame]15PLAT_BL_COMMON_SOURCES += ${CSS_ENT_BASE}/sgi_plat.c
16
Ambroise Vincentfa42c9e2019-07-04 14:58:45 +0100[diff] [blame]17BL1_SOURCES += ${SGI_CPU_SOURCES} \
18 ${RDE1EDGE_BASE}/rde1edge_err.c
Chandni Cherukuri626a52d2018-08-16 13:43:23 +0530[diff] [blame]19
Chandni Cherukuri533b5542019-02-22 16:44:49 +0530[diff] [blame]20BL2_SOURCES += ${RDE1EDGE_BASE}/rde1edge_plat.c \
21 ${RDE1EDGE_BASE}/rde1edge_security.c \
Ambroise Vincentfa42c9e2019-07-04 14:58:45 +0100[diff] [blame]22 ${RDE1EDGE_BASE}/rde1edge_err.c \
Chandni Cherukuri626a52d2018-08-16 13:43:23 +0530[diff] [blame]23 drivers/arm/tzc/tzc_dmc620.c \
24 lib/utils/mem_region.c \
25 plat/arm/common/arm_nor_psci_mem_protect.c
26
27BL31_SOURCES += ${SGI_CPU_SOURCES} \
Chandni Cherukuri533b5542019-02-22 16:44:49 +0530[diff] [blame]28 ${RDE1EDGE_BASE}/rde1edge_plat.c \
Vijayenthiran Subramaniamf5cb00f2019-12-27 19:27:57 +0530[diff] [blame]29 ${RDE1EDGE_BASE}/rde1edge_topology.c \
Chandni Cherukuri626a52d2018-08-16 13:43:23 +0530[diff] [blame]30 drivers/cfi/v2m/v2m_flash.c \
31 lib/utils/mem_region.c \
32 plat/arm/common/arm_nor_psci_mem_protect.c
33
Max Shvetsov06dba292019-12-06 11:50:12 +0000[diff] [blame]34ifeq (${TRUSTED_BOARD_BOOT}, 1)
35BL1_SOURCES += ${RDE1EDGE_BASE}/rde1edge_trusted_boot.c
36BL2_SOURCES += ${RDE1EDGE_BASE}/rde1edge_trusted_boot.c
37endif
38
Chandni Cherukuri626a52d2018-08-16 13:43:23 +0530[diff] [blame]39# Add the FDT_SOURCES and options for Dynamic Config
Manish V Badarkhe64616a52020-05-31 08:53:40 +0100[diff] [blame]40FDT_SOURCES += ${RDE1EDGE_BASE}/fdts/${PLAT}_fw_config.dts \
41 ${RDE1EDGE_BASE}/fdts/${PLAT}_tb_fw_config.dts
42FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb
43TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb
Chandni Cherukuri626a52d2018-08-16 13:43:23 +0530[diff] [blame]44
Manish V Badarkhe64616a52020-05-31 08:53:40 +0100[diff] [blame]45# Add the FW_CONFIG to FIP and specify the same to certtool
Anders Dellien3f694742020-08-23 19:32:48 +0100[diff] [blame]46$(eval $(call TOOL_ADD_PAYLOAD,${FW_CONFIG},--fw-config,${FW_CONFIG}))
Chandni Cherukuri626a52d2018-08-16 13:43:23 +0530[diff] [blame]47# Add the TB_FW_CONFIG to FIP and specify the same to certtool
Anders Dellien3f694742020-08-23 19:32:48 +0100[diff] [blame]48$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config,${TB_FW_CONFIG}))
Chandni Cherukuri626a52d2018-08-16 13:43:23 +0530[diff] [blame]49
Chandni Cherukuri533b5542019-02-22 16:44:49 +0530[diff] [blame]50FDT_SOURCES += ${RDE1EDGE_BASE}/fdts/${PLAT}_nt_fw_config.dts
Chandni Cherukuri626a52d2018-08-16 13:43:23 +0530[diff] [blame]51NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb
52
53# Add the NT_FW_CONFIG to FIP and specify the same to certtool
Anders Dellien3f694742020-08-23 19:32:48 +0100[diff] [blame]54$(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config,${NT_FW_CONFIG}))
Chandni Cherukuri626a52d2018-08-16 13:43:23 +0530[diff] [blame]55
Vijayenthiran Subramaniambc489912019-12-26 17:45:58 +0530[diff] [blame]56ifneq ($(CSS_SGI_CHIP_COUNT),1)
57 $(error "Chip count for RDE1Edge should be 1, currently set to \
58 ${CSS_SGI_CHIP_COUNT}.")
59endif
60
Aditya Angadi06402222021-03-20 12:06:15 +0530[diff] [blame]61ifneq ($(CSS_SGI_PLATFORM_VARIANT),0)
62 $(error "CSS_SGI_PLATFORM_VARIANT for RD-E1-Edge should always be 0, \
63 currently set to ${CSS_SGI_PLATFORM_VARIANT}.")
64endif
65
Chandni Cherukuri626a52d2018-08-16 13:43:23 +0530[diff] [blame]66override CTX_INCLUDE_AARCH32_REGS := 0