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git01.mediatek.com / filogic / atf / 3f69474cf094f632b70c50e8ad3328aa7d791989 / . / plat / arm / board / rde1edge / platform.mk
blob: a7c043413a1af40782280795ff643cc6604e3364 [file] [log] [blame]
Chandni Cherukuri626a52d2018-08-16 13:43:23 +0530[diff] [blame]1#
Vijayenthiran Subramaniamf5cb00f2019-12-27 19:27:57 +0530[diff] [blame]2# Copyright (c) 2018-2020, Arm Limited. All rights reserved.
Chandni Cherukuri626a52d2018-08-16 13:43:23 +0530[diff] [blame]3#
4# SPDX-License-Identifier: BSD-3-Clause
5#
6
7include plat/arm/css/sgi/sgi-common.mk
8
Chandni Cherukuri533b5542019-02-22 16:44:49 +0530[diff] [blame]9RDE1EDGE_BASE = plat/arm/board/rde1edge
Chandni Cherukuri626a52d2018-08-16 13:43:23 +0530[diff] [blame]10
Chandni Cherukuri533b5542019-02-22 16:44:49 +0530[diff] [blame]11PLAT_INCLUDES += -I${RDE1EDGE_BASE}/include/
Chandni Cherukuri626a52d2018-08-16 13:43:23 +0530[diff] [blame]12
John Tsichritzis16e6d9f2019-02-19 14:01:55 +0000[diff] [blame]13SGI_CPU_SOURCES := lib/cpus/aarch64/neoverse_e1.S
Chandni Cherukuri626a52d2018-08-16 13:43:23 +0530[diff] [blame]14
Ambroise Vincentfa42c9e2019-07-04 14:58:45 +0100[diff] [blame]15BL1_SOURCES += ${SGI_CPU_SOURCES} \
16 ${RDE1EDGE_BASE}/rde1edge_err.c
Chandni Cherukuri626a52d2018-08-16 13:43:23 +0530[diff] [blame]17
Chandni Cherukuri533b5542019-02-22 16:44:49 +0530[diff] [blame]18BL2_SOURCES += ${RDE1EDGE_BASE}/rde1edge_plat.c \
19 ${RDE1EDGE_BASE}/rde1edge_security.c \
Ambroise Vincentfa42c9e2019-07-04 14:58:45 +0100[diff] [blame]20 ${RDE1EDGE_BASE}/rde1edge_err.c \
Chandni Cherukuri626a52d2018-08-16 13:43:23 +0530[diff] [blame]21 drivers/arm/tzc/tzc_dmc620.c \
22 lib/utils/mem_region.c \
23 plat/arm/common/arm_nor_psci_mem_protect.c
24
25BL31_SOURCES += ${SGI_CPU_SOURCES} \
Chandni Cherukuri533b5542019-02-22 16:44:49 +0530[diff] [blame]26 ${RDE1EDGE_BASE}/rde1edge_plat.c \
Vijayenthiran Subramaniamf5cb00f2019-12-27 19:27:57 +0530[diff] [blame]27 ${RDE1EDGE_BASE}/rde1edge_topology.c \
Chandni Cherukuri626a52d2018-08-16 13:43:23 +0530[diff] [blame]28 drivers/cfi/v2m/v2m_flash.c \
29 lib/utils/mem_region.c \
30 plat/arm/common/arm_nor_psci_mem_protect.c
31
Max Shvetsov06dba292019-12-06 11:50:12 +0000[diff] [blame]32ifeq (${TRUSTED_BOARD_BOOT}, 1)
33BL1_SOURCES += ${RDE1EDGE_BASE}/rde1edge_trusted_boot.c
34BL2_SOURCES += ${RDE1EDGE_BASE}/rde1edge_trusted_boot.c
35endif
36
Chandni Cherukuri626a52d2018-08-16 13:43:23 +0530[diff] [blame]37# Add the FDT_SOURCES and options for Dynamic Config
Manish V Badarkhe64616a52020-05-31 08:53:40 +0100[diff] [blame]38FDT_SOURCES += ${RDE1EDGE_BASE}/fdts/${PLAT}_fw_config.dts \
39 ${RDE1EDGE_BASE}/fdts/${PLAT}_tb_fw_config.dts
40FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb
41TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb
Chandni Cherukuri626a52d2018-08-16 13:43:23 +0530[diff] [blame]42
Manish V Badarkhe64616a52020-05-31 08:53:40 +0100[diff] [blame]43# Add the FW_CONFIG to FIP and specify the same to certtool
Anders Dellien3f694742020-08-23 19:32:48 +0100[diff] [blame^]44$(eval $(call TOOL_ADD_PAYLOAD,${FW_CONFIG},--fw-config,${FW_CONFIG}))
Chandni Cherukuri626a52d2018-08-16 13:43:23 +0530[diff] [blame]45# Add the TB_FW_CONFIG to FIP and specify the same to certtool
Anders Dellien3f694742020-08-23 19:32:48 +0100[diff] [blame^]46$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config,${TB_FW_CONFIG}))
Chandni Cherukuri626a52d2018-08-16 13:43:23 +0530[diff] [blame]47
Chandni Cherukuri533b5542019-02-22 16:44:49 +0530[diff] [blame]48FDT_SOURCES += ${RDE1EDGE_BASE}/fdts/${PLAT}_nt_fw_config.dts
Chandni Cherukuri626a52d2018-08-16 13:43:23 +0530[diff] [blame]49NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb
50
51# Add the NT_FW_CONFIG to FIP and specify the same to certtool
Anders Dellien3f694742020-08-23 19:32:48 +0100[diff] [blame^]52$(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config,${NT_FW_CONFIG}))
Chandni Cherukuri626a52d2018-08-16 13:43:23 +0530[diff] [blame]53
Vijayenthiran Subramaniambc489912019-12-26 17:45:58 +0530[diff] [blame]54ifneq ($(CSS_SGI_CHIP_COUNT),1)
55 $(error "Chip count for RDE1Edge should be 1, currently set to \
56 ${CSS_SGI_CHIP_COUNT}.")
57endif
58
Chandni Cherukuri626a52d2018-08-16 13:43:23 +0530[diff] [blame]59override CTX_INCLUDE_AARCH32_REGS := 0