blob: 64ba2676de410565ae5c17fc7a60571152b8b652 [file] [log] [blame]
Jit Loon Lima7f54942023-05-17 12:26:11 +08001/*
2 * Copyright (c) 2022-2023, Intel Corporation. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef CDN_NAND_H
8#define CDN_NAND_H
9
10#include <drivers/cadence/cdns_combo_phy.h>
11
12/* NAND flash device information */
13typedef struct cnf_dev_info {
14 uint8_t type;
15 uint8_t nluns;
16 uint8_t sector_cnt;
17 uint16_t npages_per_block;
18 uint16_t sector_size;
19 uint16_t last_sector_size;
20 uint16_t page_size;
21 uint16_t spare_size;
22 uint32_t nblocks_per_lun;
23 uint32_t block_size;
24 unsigned long long total_size;
25} cnf_dev_info_t;
26
27/* Shared Macros */
28
29/* Default values */
30#define CNF_DEF_VOL_ID 0
31#define CNF_DEF_DEVICE 0
32#define CNF_DEF_TRD 0
33#define CNF_READ_SINGLE_PAGE 1
34#define CNF_DEF_DELAY_US 500
35#define CNF_READ_INT_DELAY_US 10
36
37/* Work modes */
38#define CNF_WORK_MODE_CDMA 0
39#define CNF_WORK_MODE_PIO 1
40
41/* Command types */
42#define CNF_CT_SET_FEATURE 0x0100
43#define CNF_CT_RESET_ASYNC 0x1100
44#define CNF_CT_RESET_SYNC 0x1101
45#define CNF_CT_RESET_LUN 0x1102
46#define CNF_CT_ERASE 0x1000
47#define CNF_CT_PAGE_PROGRAM 0x2100
48#define CNF_CT_PAGE_READ 0x2200
49
50/* Interrupts enable or disable */
51#define CNF_INT_EN 1
52#define CNF_INT_DIS 0
53
54/* Device types */
55#define CNF_DT_UNKNOWN 0x00
56#define CNF_DT_ONFI 0x01
57#define CNF_DT_JEDEC 0x02
58#define CNF_DT_LEGACY 0x03
59
60/* Command and status registers */
61#define CNF_CMDREG_REG_BASE SOCFPGA_NAND_REG_BASE
62
63/* DMA maximum burst size 0-127*/
64#define CNF_DMA_BURST_SIZE_MAX 127
65
66/* DMA settings register field offsets */
67#define CNF_DMA_SETTINGS_BURST 0
68#define CNF_DMA_SETTINGS_OTE 16
69#define CNF_DMA_SETTINGS_SDMA_ERR 17
70
71#define CNF_DMA_MASTER_SEL 1
72#define CNF_DMA_SLAVE_SEL 0
73
74/* DMA FIFO trigger level register field offsets */
75#define CNF_FIFO_TLEVEL_POS 0
76#define CNF_FIFO_TLEVEL_DMA_SIZE 16
77#define CNF_DMA_PREFETCH_SIZE (1024 / 8)
78
79#define CNF_GET_CTRL_BUSY(x) (x & (1 << 8))
80#define CNF_GET_INIT_COMP(x) (x & (1 << 9))
81
82/* Command register0 field offsets */
83#define CNF_CMDREG0_CT 30
84#define CNF_CMDREG0_TRD 24
85#define CNF_CMDREG0_INTR 20
86#define CNF_CMDREG0_DMA 21
87#define CNF_CMDREG0_VOL 16
88#define CNF_CMDREG0_CMD 0
89#define CNF_CMDREG4_MEM 24
90
91/* Command status register field offsets */
92#define CNF_ECMD BIT(0)
93#define CNF_EECC BIT(1)
94#define CNF_EMAX BIT(2)
95#define CNF_EDEV BIT(12)
96#define CNF_EDQS BIT(13)
97#define CNF_EFAIL BIT(14)
98#define CNF_CMPLT BIT(15)
99#define CNF_EBUS BIT(16)
100#define CNF_EDI BIT(17)
101#define CNF_EPAR BIT(18)
102#define CNF_ECTX BIT(19)
103#define CNF_EPRO BIT(20)
104#define CNF_EIDX BIT(24)
105
106#define CNF_CMDREG_CMD_REG0 0x00
107#define CNF_CMDREG_CMD_REG1 0x04
108#define CNF_CMDREG_CMD_REG2 0x08
109#define CNF_CMDREG_CMD_REG3 0x0C
110#define CNF_CMDREG_CMD_STAT_PTR 0x10
111#define CNF_CMDREG_CMD_STAT 0x14
112#define CNF_CMDREG_CMD_REG4 0x20
113#define CNF_CMDREG_CTRL_STATUS 0x118
114#define CNF_CMDREG_TRD_STATUS 0x120
115
116#define CNF_CMDREG(_reg) (CNF_CMDREG_REG_BASE \
117 + (CNF_CMDREG_##_reg))
118
119/* Controller configuration registers */
120#define CNF_LSB16_MASK 0xFFFF
121#define CNF_GET_NPAGES_PER_BLOCK(x) (x & CNF_LSB16_MASK)
122
123#define CNF_GET_SCTR_SIZE(x) (x & CNF_LSB16_MASK)
124#define CNF_GET_LAST_SCTR_SIZE(x) ((x >> 16) & CNF_LSB16_MASK)
125
126#define CNF_GET_PAGE_SIZE(x) (x & CNF_LSB16_MASK)
127#define CNF_GET_SPARE_SIZE(x) ((x >> 16) & CNF_LSB16_MASK)
128
129#define CNF_CTRLCFG_REG_BASE 0x10B80400
130#define CNF_CTRLCFG_TRANS_CFG0 0x00
131#define CNF_CTRLCFG_TRANS_CFG1 0x04
132#define CNF_CTRLCFG_LONG_POLL 0x08
133#define CNF_CTRLCFG_SHORT_POLL 0x0C
134#define CNF_CTRLCFG_DEV_STAT 0x10
135#define CNF_CTRLCFG_DEV_LAYOUT 0x24
136#define CNF_CTRLCFG_ECC_CFG0 0x28
137#define CNF_CTRLCFG_ECC_CFG1 0x2C
138#define CNF_CTRLCFG_MULTIPLANE_CFG 0x34
139#define CNF_CTRLCFG_CACHE_CFG 0x38
140#define CNF_CTRLCFG_DMA_SETTINGS 0x3C
141#define CNF_CTRLCFG_FIFO_TLEVEL 0x54
142
143#define CNF_CTRLCFG(_reg) (CNF_CTRLCFG_REG_BASE \
144 + (CNF_CTRLCFG_##_reg))
145
146/* Data integrity registers */
147#define CNF_DI_PAR_EN 0
148#define CNF_DI_CRC_EN 1
149
150#define CNF_DI_REG_BASE 0x10B80700
151#define CNF_DI_CONTROL 0x00
152#define CNF_DI_INJECT0 0x04
153#define CNF_DI_INJECT1 0x08
154#define CNF_DI_ERR_REG_ADDR 0x0C
155#define CNF_DI_INJECT2 0x10
156
157#define CNF_DI(_reg) (CNF_DI_REG_BASE \
158 + (CNF_DI_##_reg))
159
160/* Controller parameter registers */
161#define CNF_NTHREADS_MASK 0x07
162#define CNF_GET_NLUNS(x) (x & 0xFF)
163#define CNF_GET_DEV_TYPE(x) ((x >> 30) & 0x03)
164#define CNF_GET_NTHREADS(x) (1 << (x & CNF_NTHREADS_MASK))
165
166#define CNF_CTRLPARAM_REG_BASE 0x10B80800
167#define CNF_CTRLPARAM_VERSION 0x00
168#define CNF_CTRLPARAM_FEATURE 0x04
169#define CNF_CTRLPARAM_MFR_ID 0x08
170#define CNF_CTRLPARAM_DEV_AREA 0x0C
171#define CNF_CTRLPARAM_DEV_PARAMS0 0x10
172#define CNF_CTRLPARAM_DEV_PARAMS1 0x14
173#define CNF_CTRLPARAM_DEV_FEATUERS 0x18
174#define CNF_CTRLPARAM_DEV_BLOCKS_PLUN 0x1C
175
176#define CNF_CTRLPARAM(_reg) (CNF_CTRLPARAM_REG_BASE \
177 + (CNF_CTRLPARAM_##_reg))
178
179/* Protection mechanism registers */
180#define CNF_PROT_REG_BASE 0x10B80900
181#define CNF_PROT_CTRL0 0x00
182#define CNF_PROT_DOWN0 0x04
183#define CNF_PROT_UP0 0x08
184#define CNF_PROT_CTRL1 0x10
185#define CNF_PROT_DOWN1 0x14
186#define CNF_PROT_UP1 0x18
187
188#define CNF_PROT(_reg) (CNF_PROT_REG_BASE \
189 + (CNF_PROT_##_reg))
190
191/* Mini controller registers */
192#define CNF_MINICTRL_REG_BASE 0x10B81000
193
194/* Operation work modes */
195#define CNF_OPR_WORK_MODE_SDR 0
196#define CNF_OPR_WORK_MODE_NVDDR 1
197#define CNF_OPR_WORK_MODE_TOGGLE_NVDDR2_3 2
198#define CNF_OPR_WORK_MODE_RES 3
199
200/* Mini controller common settings register field offsets */
201#define CNF_CMN_SETTINGS_WR_WUP 20
202#define CNF_CMN_SETTINGS_RD_WUP 16
203#define CNF_CMN_SETTINGS_DEV16 8
204#define CNF_CMN_SETTINGS_OPR 0
205
206/* Async mode register field offsets */
207#define CNF_ASYNC_TIMINGS_TRH 24
208#define CNF_ASYNC_TIMINGS_TRP 16
209#define CNF_ASYNC_TIMINGS_TWH 8
210#define CNF_ASYNC_TIMINGS_TWP 0
211
212/* Mini controller DLL PHY controller register field offsets */
213#define CNF_DLL_PHY_RST_N 24
214#define CNF_DLL_PHY_EXT_WR_MODE 17
215#define CNF_DLL_PHY_EXT_RD_MODE 16
216
217#define CNF_MINICTRL_WP_SETTINGS 0x00
218#define CNF_MINICTRL_RBN_SETTINGS 0x04
219#define CNF_MINICTRL_CMN_SETTINGS 0x08
220#define CNF_MINICTRL_SKIP_BYTES_CFG 0x0C
221#define CNF_MINICTRL_SKIP_BYTES_OFFSET 0x10
222#define CNF_MINICTRL_TOGGLE_TIMINGS0 0x14
223#define CNF_MINICTRL_TOGGLE_TIMINGS1 0x18
224#define CNF_MINICTRL_ASYNC_TOGGLE_TIMINGS 0x1C
225#define CNF_MINICTRL_SYNC_TIMINGS 0x20
226#define CNF_MINICTRL_DLL_PHY_CTRL 0x34
227
228#define CNF_MINICTRL(_reg) (CNF_MINICTRL_REG_BASE \
229 + (CNF_MINICTRL_##_reg))
230
231/*
232 * @brief Nand IO MTD initialization routine
233 *
234 * @total_size: [out] Total size of the NAND flash device
235 * @erase_size: [out] Minimum erase size of the NAND flash device
236 * Return: 0 on success, a negative errno on failure
237 */
238int cdns_nand_init_mtd(unsigned long long *total_size,
239 unsigned int *erase_size);
240
241/*
242 * @brief Read bytes from the NAND flash device
243 *
244 * @offset: Byte offset to read from in device
245 * @buffer: [out] Bytes read from device
246 * @length: Number of bytes to read
247 * @out_length: [out] Number of bytes read from device
248 * Return: 0 on success, a negative errno on failure
249 */
250int cdns_nand_read(unsigned int offset, uintptr_t buffer,
251 size_t length, size_t *out_length);
252
253/* NAND Flash Controller/Host initialization */
254int cdns_nand_host_init(void);
255
256#endif