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Johann Neuhauser7e967d92022-02-16 17:12:34 +01001// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
2/*
3 * Copyright (C) 2019-2020 Marek Vasut <marex@denx.de>
4 * Copyright (C) 2022 DH electronics GmbH
Yann Gautierc55e2ee2023-10-18 14:17:04 +02005 * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
Johann Neuhauser7e967d92022-02-16 17:12:34 +01006 */
7
8#include "stm32mp15-pinctrl.dtsi"
9#include "stm32mp15xxaa-pinctrl.dtsi"
10#include <dt-bindings/clock/stm32mp1-clksrc.h>
11#include "stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi"
12
13/ {
14 memory@c0000000 {
15 device_type = "memory";
16 reg = <0xC0000000 0x40000000>;
17 };
18};
19
20&bsec {
21 board_id: board_id@ec {
22 reg = <0xec 0x4>;
23 st,non-secure-otp;
24 };
25};
26
Johann Neuhausera5ef16a2022-07-08 15:22:05 +020027&cpu0 {
Johann Neuhauser7e967d92022-02-16 17:12:34 +010028 cpu-supply = <&vddcore>;
29};
30
Johann Neuhausera5ef16a2022-07-08 15:22:05 +020031&cpu1 {
Johann Neuhauser7e967d92022-02-16 17:12:34 +010032 cpu-supply = <&vddcore>;
33};
34
35&hash1 {
36 status = "okay";
37};
38
39&i2c4 {
40 pinctrl-names = "default";
41 pinctrl-0 = <&i2c4_pins_a>;
42 i2c-scl-rising-time-ns = <185>;
43 i2c-scl-falling-time-ns = <20>;
44 status = "okay";
45
46 pmic: stpmic@33 {
47 compatible = "st,stpmic1";
48 reg = <0x33>;
49 interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
50 interrupt-controller;
51 #interrupt-cells = <2>;
52 status = "okay";
53
54 regulators {
55 compatible = "st,stpmic1-regulators";
56 ldo1-supply = <&v3v3>;
57 ldo2-supply = <&v3v3>;
58 ldo3-supply = <&vdd_ddr>;
59 ldo5-supply = <&v3v3>;
60 ldo6-supply = <&v3v3>;
61 pwr_sw1-supply = <&bst_out>;
62 pwr_sw2-supply = <&bst_out>;
63
64 vddcore: buck1 {
65 regulator-name = "vddcore";
66 regulator-min-microvolt = <1200000>;
67 regulator-max-microvolt = <1350000>;
68 regulator-always-on;
69 regulator-initial-mode = <0>;
70 regulator-over-current-protection;
71 };
72
73 vdd_ddr: buck2 {
74 regulator-name = "vdd_ddr";
75 regulator-min-microvolt = <1350000>;
76 regulator-max-microvolt = <1350000>;
77 regulator-always-on;
78 regulator-initial-mode = <0>;
79 regulator-over-current-protection;
80 };
81
82 vdd: buck3 {
83 regulator-name = "vdd";
84 regulator-min-microvolt = <3300000>;
85 regulator-max-microvolt = <3300000>;
86 regulator-always-on;
87 st,mask-reset;
88 regulator-initial-mode = <0>;
89 regulator-over-current-protection;
90 };
91
92 v3v3: buck4 {
93 regulator-name = "v3v3";
94 regulator-min-microvolt = <3300000>;
95 regulator-max-microvolt = <3300000>;
96 regulator-always-on;
97 regulator-over-current-protection;
98 regulator-initial-mode = <0>;
99 };
100
101 vdda: ldo1 {
102 regulator-name = "vdda";
103 regulator-min-microvolt = <2900000>;
104 regulator-max-microvolt = <2900000>;
105 regulator-always-on;
106 };
107
108 v2v8: ldo2 {
109 regulator-name = "v2v8";
110 regulator-min-microvolt = <2800000>;
111 regulator-max-microvolt = <2800000>;
112 };
113
114 vtt_ddr: ldo3 {
115 regulator-name = "vtt_ddr";
116 regulator-always-on;
117 regulator-over-current-protection;
118 st,regulator-sink-source;
119 };
120
121 vdd_usb: ldo4 {
122 regulator-name = "vdd_usb";
123 regulator-min-microvolt = <3300000>;
124 regulator-max-microvolt = <3300000>;
125 };
126
127 vdd_sd: ldo5 {
128 regulator-name = "vdd_sd";
129 regulator-min-microvolt = <2900000>;
130 regulator-max-microvolt = <2900000>;
131 regulator-boot-on;
132 };
133
134 v1v8: ldo6 {
135 regulator-name = "v1v8";
136 regulator-min-microvolt = <1800000>;
137 regulator-max-microvolt = <1800000>;
138 };
139
140 vref_ddr: vref_ddr {
141 regulator-name = "vref_ddr";
142 regulator-always-on;
143 };
144
145 bst_out: boost {
146 regulator-name = "bst_out";
147 };
148
149 vbus_otg: pwr_sw1 {
150 regulator-name = "vbus_otg";
151 };
152
153 vbus_sw: pwr_sw2 {
154 regulator-name = "vbus_sw";
155 regulator-active-discharge = <1>;
156 };
157 };
158 };
159};
160
161&iwdg2 {
162 timeout-sec = <32>;
163 status = "okay";
Johann Neuhauser7e967d92022-02-16 17:12:34 +0100164};
165
166&pwr_regulators {
167 vdd-supply = <&vdd>;
168 vdd_3v3_usbfs-supply = <&vdd_usb>;
169};
170
171&qspi {
172 pinctrl-names = "default";
Yann Gautierc55e2ee2023-10-18 14:17:04 +0200173 pinctrl-0 = <&qspi_clk_pins_a
174 &qspi_bk1_pins_a
175 &qspi_cs1_pins_a>;
Johann Neuhauser7e967d92022-02-16 17:12:34 +0100176 reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
177 #address-cells = <1>;
178 #size-cells = <0>;
179 status = "okay";
180
181 flash0: flash@0 {
182 compatible = "jedec,spi-nor";
183 reg = <0>;
184 spi-rx-bus-width = <4>;
185 spi-max-frequency = <108000000>;
186 #address-cells = <1>;
187 #size-cells = <1>;
188 };
189};
190
191&rcc {
Johann Neuhauser7e967d92022-02-16 17:12:34 +0100192 st,clksrc = <
193 CLK_MPU_PLL1P
194 CLK_AXI_PLL2P
195 CLK_MCU_PLL3P
196 CLK_PLL12_HSE
197 CLK_PLL3_HSE
198 CLK_PLL4_HSE
199 CLK_RTC_LSE
200 CLK_MCO1_DISABLED
201 CLK_MCO2_PLL4P
202 >;
203
204 st,clkdiv = <
205 1 /*MPU*/
206 0 /*AXI*/
207 0 /*MCU*/
208 1 /*APB1*/
209 1 /*APB2*/
210 1 /*APB3*/
211 1 /*APB4*/
212 2 /*APB5*/
213 23 /*RTC*/
214 0 /*MCO1*/
215 1 /*MCO2*/
216 >;
217
218 st,pkcs = <
219 CLK_CKPER_HSE
220 CLK_FMC_ACLK
221 CLK_QSPI_ACLK
222 CLK_ETH_PLL4P
223 CLK_SDMMC12_PLL4P
224 CLK_DSI_DSIPLL
225 CLK_STGEN_HSE
226 CLK_USBPHY_HSE
227 CLK_SPI2S1_PLL3Q
228 CLK_SPI2S23_PLL3Q
229 CLK_SPI45_HSI
230 CLK_SPI6_HSI
231 CLK_I2C46_HSI
232 CLK_SDMMC3_PLL4P
233 CLK_USBO_USBPHY
234 CLK_ADC_CKPER
235 CLK_CEC_LSE
236 CLK_I2C12_HSI
237 CLK_I2C35_HSI
238 CLK_UART1_HSI
239 CLK_UART24_HSI
240 CLK_UART35_HSI
241 CLK_UART6_HSI
242 CLK_UART78_HSI
243 CLK_SPDIF_PLL4P
244 CLK_FDCAN_PLL4R
245 CLK_SAI1_PLL3Q
246 CLK_SAI2_PLL3Q
247 CLK_SAI3_PLL3Q
248 CLK_SAI4_PLL3Q
249 CLK_RNG1_LSI
250 CLK_RNG2_LSI
251 CLK_LPTIM1_PCLK1
252 CLK_LPTIM23_PCLK3
253 CLK_LPTIM45_LSE
254 >;
255
256 /* VCO = 1300.0 MHz => P = 650 (CPU) */
257 pll1: st,pll@0 {
258 compatible = "st,stm32mp1-pll";
259 reg = <0>;
260 cfg = <2 80 0 0 0 PQR(1,0,0)>;
261 frac = <0x800>;
262 };
263
264 /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
265 pll2: st,pll@1 {
266 compatible = "st,stm32mp1-pll";
267 reg = <1>;
268 cfg = <2 65 1 0 0 PQR(1,1,1)>;
269 frac = <0x1400>;
270 };
271
272 /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
273 pll3: st,pll@2 {
274 compatible = "st,stm32mp1-pll";
275 reg = <2>;
276 cfg = <1 33 1 16 36 PQR(1,1,1)>;
277 frac = <0x1a04>;
278 };
279
280 /* VCO = 600.0 MHz => P = 50, Q = 50, R = 50 */
281 pll4: st,pll@3 {
282 compatible = "st,stm32mp1-pll";
283 reg = <3>;
284 cfg = <1 49 5 11 11 PQR(1,1,1)>;
285 };
286};
287
288&rng1 {
289 status = "okay";
290};
291
292&rtc {
293 status = "okay";
294};
295
296&sdmmc1 {
297 pinctrl-names = "default";
298 pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
299 disable-wp;
300 st,sig-dir;
301 st,neg-edge;
302 bus-width = <4>;
303 vmmc-supply = <&vdd_sd>;
304 status = "okay";
305};
306
307&sdmmc1_b4_pins_a {
308 /*
309 * SD bus pull-up resistors:
310 * - optional on SoMs with SD voltage translator
311 * - mandatory on SoMs without SD voltage translator
312 */
313 pins1 {
314 bias-pull-up;
315 };
316 pins2 {
317 bias-pull-up;
318 };
319};
320
321&sdmmc2 {
322 pinctrl-names = "default";
323 pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
324 non-removable;
325 no-sd;
326 no-sdio;
327 st,neg-edge;
328 bus-width = <8>;
329 vmmc-supply = <&v3v3>;
330 vqmmc-supply = <&v3v3>;
331 mmc-ddr-3_3v;
332 status = "okay";
333};
334
335&uart4 {
336 pinctrl-names = "default";
337 pinctrl-0 = <&uart4_pins_a>;
338 status = "okay";
339};