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Dan Handley9df48042015-03-19 18:58:55 +00001/*
Summer Qin9db8f2e2017-04-24 16:49:28 +01002 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Dan Handley9df48042015-03-19 18:58:55 +00005 */
6#include <arm_def.h>
7#include <plat_arm.h>
8
9/*
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +010010 * Table of memory regions for different BL stages to map using the MMU.
11 * This doesn't include Trusted SRAM as arm_setup_page_tables() already
12 * takes care of mapping it.
Dan Handley9df48042015-03-19 18:58:55 +000013 */
Masahiro Yamada441bfdd2016-12-25 23:36:24 +090014#ifdef IMAGE_BL1
Dan Handley9df48042015-03-19 18:58:55 +000015const mmap_region_t plat_arm_mmap[] = {
16 ARM_MAP_SHARED_RAM,
Juan Castillob6132f12015-10-06 14:01:35 +010017 V2M_MAP_FLASH0_RO,
Dan Handley9df48042015-03-19 18:58:55 +000018 V2M_MAP_IOFPGA,
19 CSS_MAP_DEVICE,
20 SOC_CSS_MAP_DEVICE,
Yatharth Kochar736a3bf2015-10-11 14:14:55 +010021#if TRUSTED_BOARD_BOOT
Sandrine Bailleuxd9160a52017-05-26 15:48:10 +010022 /* Map DRAM to authenticate NS_BL2U image. */
Yatharth Kochar736a3bf2015-10-11 14:14:55 +010023 ARM_MAP_NS_DRAM1,
24#endif
Dan Handley9df48042015-03-19 18:58:55 +000025 {0}
26};
27#endif
Masahiro Yamada441bfdd2016-12-25 23:36:24 +090028#ifdef IMAGE_BL2
Dan Handley9df48042015-03-19 18:58:55 +000029const mmap_region_t plat_arm_mmap[] = {
30 ARM_MAP_SHARED_RAM,
Juan Castillob6132f12015-10-06 14:01:35 +010031 V2M_MAP_FLASH0_RO,
Dan Handley9df48042015-03-19 18:58:55 +000032 V2M_MAP_IOFPGA,
33 CSS_MAP_DEVICE,
34 SOC_CSS_MAP_DEVICE,
35 ARM_MAP_NS_DRAM1,
36 ARM_MAP_TSP_SEC_MEM,
Summer Qin9db8f2e2017-04-24 16:49:28 +010037#ifdef SPD_opteed
38 ARM_OPTEE_PAGEABLE_LOAD_MEM,
39#endif
Dan Handley9df48042015-03-19 18:58:55 +000040 {0}
41};
42#endif
Masahiro Yamada441bfdd2016-12-25 23:36:24 +090043#ifdef IMAGE_BL2U
Yatharth Kochar3a11eda2015-10-14 15:28:11 +010044const mmap_region_t plat_arm_mmap[] = {
45 ARM_MAP_SHARED_RAM,
46 CSS_MAP_DEVICE,
47 SOC_CSS_MAP_DEVICE,
48 {0}
49};
50#endif
Masahiro Yamada441bfdd2016-12-25 23:36:24 +090051#ifdef IMAGE_BL31
Dan Handley9df48042015-03-19 18:58:55 +000052const mmap_region_t plat_arm_mmap[] = {
53 ARM_MAP_SHARED_RAM,
54 V2M_MAP_IOFPGA,
55 CSS_MAP_DEVICE,
Soby Mathewcbafd7a2016-11-14 12:44:32 +000056#if CSS_USE_SCMI_DRIVER
57 /*
58 * The SCMI payload area is currently in the Non Secure SRAM. This is
59 * a potential security risk but this will be resolved once SCP
60 * completely replaces SCPI with SCMI as the only communication
61 * protocol.
62 */
63 CSS_MAP_NSRAM,
64#endif
Dan Handley9df48042015-03-19 18:58:55 +000065 SOC_CSS_MAP_DEVICE,
66 {0}
67};
68#endif
Masahiro Yamada441bfdd2016-12-25 23:36:24 +090069#ifdef IMAGE_BL32
Dan Handley9df48042015-03-19 18:58:55 +000070const mmap_region_t plat_arm_mmap[] = {
Yatharth Kochar2694cba2016-11-14 12:00:41 +000071#ifdef AARCH32
72 ARM_MAP_SHARED_RAM,
73#endif
Dan Handley9df48042015-03-19 18:58:55 +000074 V2M_MAP_IOFPGA,
75 CSS_MAP_DEVICE,
76 SOC_CSS_MAP_DEVICE,
77 {0}
78};
79#endif
80
81ARM_CASSERT_MMAP