Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef __PLAT_PRIVATE_H__ |
| 8 | #define __PLAT_PRIVATE_H__ |
| 9 | |
| 10 | #ifndef __ASSEMBLY__ |
| 11 | #include <mmio.h> |
| 12 | #include <stdint.h> |
| 13 | #include <xlat_tables.h> |
Tony Xie | 42e113e | 2016-07-16 11:16:51 +0800 | [diff] [blame] | 14 | #include <psci.h> |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 15 | |
Caesar Wang | d90f43e | 2016-10-11 09:36:00 +0800 | [diff] [blame] | 16 | #define __sramdata __attribute__((section(".sram.data"))) |
| 17 | #define __sramconst __attribute__((section(".sram.rodata"))) |
Lin Huang | 30e4339 | 2017-05-04 16:02:45 +0800 | [diff] [blame] | 18 | #define __sramfunc __attribute__((section(".sram.text"))) |
| 19 | |
| 20 | #define __pmusramdata __attribute__((section(".pmusram.data"))) |
| 21 | #define __pmusramconst __attribute__((section(".pmusram.rodata"))) |
| 22 | #define __pmusramfunc __attribute__((section(".pmusram.text"))) |
Caesar Wang | d90f43e | 2016-10-11 09:36:00 +0800 | [diff] [blame] | 23 | |
| 24 | extern uint32_t __bl31_sram_text_start, __bl31_sram_text_end; |
| 25 | extern uint32_t __bl31_sram_data_start, __bl31_sram_data_end; |
Lin Huang | 30e4339 | 2017-05-04 16:02:45 +0800 | [diff] [blame] | 26 | extern uint32_t __bl31_sram_stack_start, __bl31_sram_stack_end; |
Lin Huang | 88dd123 | 2017-05-16 16:40:46 +0800 | [diff] [blame] | 27 | extern uint32_t __bl31_sram_text_real_end, __bl31_sram_data_real_end; |
Xing Zheng | 93280b7 | 2016-10-26 21:25:26 +0800 | [diff] [blame] | 28 | extern uint32_t __sram_incbin_start, __sram_incbin_end; |
Lin Huang | 88dd123 | 2017-05-16 16:40:46 +0800 | [diff] [blame] | 29 | extern uint32_t __sram_incbin_real_end; |
Caesar Wang | d90f43e | 2016-10-11 09:36:00 +0800 | [diff] [blame] | 30 | |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 31 | |
| 32 | /****************************************************************************** |
| 33 | * The register have write-mask bits, it is mean, if you want to set the bits, |
| 34 | * you needs set the write-mask bits at the same time, |
| 35 | * The write-mask bits is in high 16-bits. |
| 36 | * The fllowing macro definition helps access write-mask bits reg efficient! |
| 37 | ******************************************************************************/ |
| 38 | #define REG_MSK_SHIFT 16 |
| 39 | |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 40 | #ifndef WMSK_BIT |
| 41 | #define WMSK_BIT(nr) BIT((nr) + REG_MSK_SHIFT) |
| 42 | #endif |
| 43 | |
| 44 | /* set one bit with write mask */ |
| 45 | #ifndef BIT_WITH_WMSK |
| 46 | #define BIT_WITH_WMSK(nr) (BIT(nr) | WMSK_BIT(nr)) |
| 47 | #endif |
| 48 | |
| 49 | #ifndef BITS_SHIFT |
| 50 | #define BITS_SHIFT(bits, shift) (bits << (shift)) |
| 51 | #endif |
| 52 | |
| 53 | #ifndef BITS_WITH_WMASK |
Caesar Wang | 59e41b5 | 2016-04-10 14:11:07 +0800 | [diff] [blame] | 54 | #define BITS_WITH_WMASK(bits, msk, shift)\ |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 55 | (BITS_SHIFT(bits, shift) | BITS_SHIFT(msk, (shift + REG_MSK_SHIFT))) |
| 56 | #endif |
| 57 | |
| 58 | /****************************************************************************** |
| 59 | * Function and variable prototypes |
| 60 | *****************************************************************************/ |
| 61 | void plat_configure_mmu_el3(unsigned long total_base, |
| 62 | unsigned long total_size, |
| 63 | unsigned long, |
| 64 | unsigned long, |
| 65 | unsigned long, |
| 66 | unsigned long); |
| 67 | |
| 68 | void plat_cci_init(void); |
| 69 | void plat_cci_enable(void); |
| 70 | void plat_cci_disable(void); |
| 71 | |
| 72 | void plat_delay_timer_init(void); |
| 73 | |
Caesar Wang | 3e3c5b0 | 2016-05-25 19:03:04 +0800 | [diff] [blame] | 74 | void params_early_setup(void *plat_params_from_bl2); |
| 75 | |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 76 | void plat_rockchip_gic_driver_init(void); |
| 77 | void plat_rockchip_gic_init(void); |
| 78 | void plat_rockchip_gic_cpuif_enable(void); |
| 79 | void plat_rockchip_gic_cpuif_disable(void); |
| 80 | void plat_rockchip_gic_pcpu_init(void); |
| 81 | |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 82 | void plat_rockchip_pmu_init(void); |
| 83 | void plat_rockchip_soc_init(void); |
Tony Xie | 42e113e | 2016-07-16 11:16:51 +0800 | [diff] [blame] | 84 | uintptr_t plat_get_sec_entrypoint(void); |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 85 | |
Caesar Wang | 59e41b5 | 2016-04-10 14:11:07 +0800 | [diff] [blame] | 86 | void platform_cpu_warmboot(void); |
| 87 | |
Caesar Wang | ef18007 | 2016-09-10 02:43:15 +0800 | [diff] [blame] | 88 | struct gpio_info *plat_get_rockchip_gpio_reset(void); |
| 89 | struct gpio_info *plat_get_rockchip_gpio_poweroff(void); |
| 90 | struct gpio_info *plat_get_rockchip_suspend_gpio(uint32_t *count); |
Caesar Wang | 5045a1c | 2016-09-10 02:47:53 +0800 | [diff] [blame] | 91 | struct apio_info *plat_get_rockchip_suspend_apio(void); |
Caesar Wang | 038f6aa | 2016-05-25 19:21:43 +0800 | [diff] [blame] | 92 | void plat_rockchip_gpio_init(void); |
| 93 | |
tony.xie | 422d51c | 2017-03-01 11:05:17 +0800 | [diff] [blame] | 94 | int rockchip_soc_cores_pwr_dm_on(unsigned long mpidr, uint64_t entrypoint); |
| 95 | int rockchip_soc_hlvl_pwr_dm_off(uint32_t lvl, |
| 96 | plat_local_state_t lvl_state); |
| 97 | int rockchip_soc_cores_pwr_dm_off(void); |
| 98 | int rockchip_soc_sys_pwr_dm_suspend(void); |
| 99 | int rockchip_soc_cores_pwr_dm_suspend(void); |
| 100 | int rockchip_soc_hlvl_pwr_dm_suspend(uint32_t lvl, |
| 101 | plat_local_state_t lvl_state); |
| 102 | int rockchip_soc_hlvl_pwr_dm_on_finish(uint32_t lvl, |
| 103 | plat_local_state_t lvl_state); |
| 104 | int rockchip_soc_cores_pwr_dm_on_finish(void); |
| 105 | int rockchip_soc_sys_pwr_dm_resume(void); |
| 106 | |
| 107 | int rockchip_soc_hlvl_pwr_dm_resume(uint32_t lvl, |
| 108 | plat_local_state_t lvl_state); |
| 109 | int rockchip_soc_cores_pwr_dm_resume(void); |
| 110 | void __dead2 rockchip_soc_soft_reset(void); |
| 111 | void __dead2 rockchip_soc_system_off(void); |
| 112 | void __dead2 rockchip_soc_cores_pd_pwr_dn_wfi( |
| 113 | const psci_power_state_t *target_state); |
| 114 | void __dead2 rockchip_soc_sys_pd_pwr_dn_wfi(void); |
| 115 | |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 116 | extern const unsigned char rockchip_power_domain_tree_desc[]; |
| 117 | |
Lin Huang | 30e4339 | 2017-05-04 16:02:45 +0800 | [diff] [blame] | 118 | extern void *pmu_cpuson_entrypoint; |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 119 | extern uint64_t cpuson_entry_point[PLATFORM_CORE_COUNT]; |
| 120 | extern uint32_t cpuson_flags[PLATFORM_CORE_COUNT]; |
| 121 | |
| 122 | extern const mmap_region_t plat_rk_mmap[]; |
Caesar Wang | d90f43e | 2016-10-11 09:36:00 +0800 | [diff] [blame] | 123 | |
Lin Huang | 30e4339 | 2017-05-04 16:02:45 +0800 | [diff] [blame] | 124 | void rockchip_plat_mmu_el3(void); |
Caesar Wang | d90f43e | 2016-10-11 09:36:00 +0800 | [diff] [blame] | 125 | |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 126 | #endif /* __ASSEMBLY__ */ |
| 127 | |
Tony Xie | 42e113e | 2016-07-16 11:16:51 +0800 | [diff] [blame] | 128 | /****************************************************************************** |
| 129 | * cpu up status |
| 130 | * The bits of macro value is not more than 12 bits for cmp instruction! |
| 131 | ******************************************************************************/ |
| 132 | #define PMU_CPU_HOTPLUG 0xf00 |
| 133 | #define PMU_CPU_AUTO_PWRDN 0xf0 |
| 134 | #define PMU_CLST_RET 0xa5 |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 135 | |
| 136 | #endif /* __PLAT_PRIVATE_H__ */ |