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Varun Wadekarb316e242015-05-19 16:48:04 +05301/*
Anthony Zhou59fd6152017-03-13 15:34:08 +08002 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
Varun Wadekarb316e242015-05-19 16:48:04 +05303 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Varun Wadekarb316e242015-05-19 16:48:04 +05305 */
6
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +00007#ifndef FLOWCTRL_H
8#define FLOWCTRL_H
Varun Wadekarb316e242015-05-19 16:48:04 +05309
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010#include <lib/mmio.h>
11
Varun Wadekarb316e242015-05-19 16:48:04 +053012#include <tegra_def.h>
13
Anthony Zhou59fd6152017-03-13 15:34:08 +080014#define FLOWCTRL_HALT_CPU0_EVENTS 0x0U
15#define FLOWCTRL_WAITEVENT (2U << 29)
16#define FLOWCTRL_WAIT_FOR_INTERRUPT (4U << 29)
17#define FLOWCTRL_JTAG_RESUME (1U << 28)
18#define FLOWCTRL_HALT_SCLK (1U << 27)
19#define FLOWCTRL_HALT_LIC_IRQ (1U << 11)
20#define FLOWCTRL_HALT_LIC_FIQ (1U << 10)
21#define FLOWCTRL_HALT_GIC_IRQ (1U << 9)
22#define FLOWCTRL_HALT_GIC_FIQ (1U << 8)
23#define FLOWCTRL_HALT_BPMP_EVENTS 0x4U
24#define FLOWCTRL_CPU0_CSR 0x8U
25#define FLOW_CTRL_CSR_PWR_OFF_STS (1U << 16)
26#define FLOWCTRL_CSR_INTR_FLAG (1U << 15)
27#define FLOWCTRL_CSR_EVENT_FLAG (1U << 14)
28#define FLOWCTRL_CSR_IMMEDIATE_WAKE (1U << 3)
29#define FLOWCTRL_CSR_ENABLE (1U << 0)
30#define FLOWCTRL_HALT_CPU1_EVENTS 0x14U
31#define FLOWCTRL_CPU1_CSR 0x18U
32#define FLOWCTRL_CC4_CORE0_CTRL 0x6cU
33#define FLOWCTRL_WAIT_WFI_BITMAP 0x100U
34#define FLOWCTRL_L2_FLUSH_CONTROL 0x94U
35#define FLOWCTRL_BPMP_CLUSTER_CONTROL 0x98U
36#define FLOWCTRL_BPMP_CLUSTER_PWRON_LOCK (1U << 2)
Varun Wadekarb316e242015-05-19 16:48:04 +053037
Anthony Zhou59fd6152017-03-13 15:34:08 +080038#define FLOWCTRL_ENABLE_EXT 12U
39#define FLOWCTRL_ENABLE_EXT_MASK 3U
40#define FLOWCTRL_PG_CPU_NONCPU 0x1U
41#define FLOWCTRL_TURNOFF_CPURAIL 0x2U
Varun Wadekarb316e242015-05-19 16:48:04 +053042
43static inline uint32_t tegra_fc_read_32(uint32_t off)
44{
45 return mmio_read_32(TEGRA_FLOWCTRL_BASE + off);
46}
47
48static inline void tegra_fc_write_32(uint32_t off, uint32_t val)
49{
50 mmio_write_32(TEGRA_FLOWCTRL_BASE + off, val);
51}
52
Varun Wadekarb316e242015-05-19 16:48:04 +053053void tegra_fc_cluster_idle(uint32_t midr);
Varun Wadekarb2baa892015-08-27 10:25:29 +053054void tegra_fc_cpu_powerdn(uint32_t mpidr);
Varun Wadekarb316e242015-05-19 16:48:04 +053055void tegra_fc_cluster_powerdn(uint32_t midr);
56void tegra_fc_soc_powerdn(uint32_t midr);
57void tegra_fc_cpu_on(int cpu);
58void tegra_fc_cpu_off(int cpu);
59void tegra_fc_lock_active_cluster(void);
60void tegra_fc_reset_bpmp(void);
61
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +000062#endif /* FLOWCTRL_H */