Tegra: fix trivial misra issues
Not having U or ULL as a suffix for these enums causes
a lot of unnecessary MISRA issues. This patch adds U or
ULL suffix to these common enums to reduce number of
MISRA issues.
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
diff --git a/plat/nvidia/tegra/include/drivers/flowctrl.h b/plat/nvidia/tegra/include/drivers/flowctrl.h
index 23909e8..17145e8 100644
--- a/plat/nvidia/tegra/include/drivers/flowctrl.h
+++ b/plat/nvidia/tegra/include/drivers/flowctrl.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -34,34 +34,34 @@
#include <mmio.h>
#include <tegra_def.h>
-#define FLOWCTRL_HALT_CPU0_EVENTS 0x0
-#define FLOWCTRL_WAITEVENT (2 << 29)
-#define FLOWCTRL_WAIT_FOR_INTERRUPT (4 << 29)
-#define FLOWCTRL_JTAG_RESUME (1 << 28)
-#define FLOWCTRL_HALT_SCLK (1 << 27)
-#define FLOWCTRL_HALT_LIC_IRQ (1 << 11)
-#define FLOWCTRL_HALT_LIC_FIQ (1 << 10)
-#define FLOWCTRL_HALT_GIC_IRQ (1 << 9)
-#define FLOWCTRL_HALT_GIC_FIQ (1 << 8)
-#define FLOWCTRL_HALT_BPMP_EVENTS 0x4
-#define FLOWCTRL_CPU0_CSR 0x8
-#define FLOW_CTRL_CSR_PWR_OFF_STS (1 << 16)
-#define FLOWCTRL_CSR_INTR_FLAG (1 << 15)
-#define FLOWCTRL_CSR_EVENT_FLAG (1 << 14)
-#define FLOWCTRL_CSR_IMMEDIATE_WAKE (1 << 3)
-#define FLOWCTRL_CSR_ENABLE (1 << 0)
-#define FLOWCTRL_HALT_CPU1_EVENTS 0x14
-#define FLOWCTRL_CPU1_CSR 0x18
-#define FLOWCTRL_CC4_CORE0_CTRL 0x6c
-#define FLOWCTRL_WAIT_WFI_BITMAP 0x100
-#define FLOWCTRL_L2_FLUSH_CONTROL 0x94
-#define FLOWCTRL_BPMP_CLUSTER_CONTROL 0x98
-#define FLOWCTRL_BPMP_CLUSTER_PWRON_LOCK (1 << 2)
+#define FLOWCTRL_HALT_CPU0_EVENTS 0x0U
+#define FLOWCTRL_WAITEVENT (2U << 29)
+#define FLOWCTRL_WAIT_FOR_INTERRUPT (4U << 29)
+#define FLOWCTRL_JTAG_RESUME (1U << 28)
+#define FLOWCTRL_HALT_SCLK (1U << 27)
+#define FLOWCTRL_HALT_LIC_IRQ (1U << 11)
+#define FLOWCTRL_HALT_LIC_FIQ (1U << 10)
+#define FLOWCTRL_HALT_GIC_IRQ (1U << 9)
+#define FLOWCTRL_HALT_GIC_FIQ (1U << 8)
+#define FLOWCTRL_HALT_BPMP_EVENTS 0x4U
+#define FLOWCTRL_CPU0_CSR 0x8U
+#define FLOW_CTRL_CSR_PWR_OFF_STS (1U << 16)
+#define FLOWCTRL_CSR_INTR_FLAG (1U << 15)
+#define FLOWCTRL_CSR_EVENT_FLAG (1U << 14)
+#define FLOWCTRL_CSR_IMMEDIATE_WAKE (1U << 3)
+#define FLOWCTRL_CSR_ENABLE (1U << 0)
+#define FLOWCTRL_HALT_CPU1_EVENTS 0x14U
+#define FLOWCTRL_CPU1_CSR 0x18U
+#define FLOWCTRL_CC4_CORE0_CTRL 0x6cU
+#define FLOWCTRL_WAIT_WFI_BITMAP 0x100U
+#define FLOWCTRL_L2_FLUSH_CONTROL 0x94U
+#define FLOWCTRL_BPMP_CLUSTER_CONTROL 0x98U
+#define FLOWCTRL_BPMP_CLUSTER_PWRON_LOCK (1U << 2)
-#define FLOWCTRL_ENABLE_EXT 12
-#define FLOWCTRL_ENABLE_EXT_MASK 3
-#define FLOWCTRL_PG_CPU_NONCPU 0x1
-#define FLOWCTRL_TURNOFF_CPURAIL 0x2
+#define FLOWCTRL_ENABLE_EXT 12U
+#define FLOWCTRL_ENABLE_EXT_MASK 3U
+#define FLOWCTRL_PG_CPU_NONCPU 0x1U
+#define FLOWCTRL_TURNOFF_CPURAIL 0x2U
static inline uint32_t tegra_fc_read_32(uint32_t off)
{