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Nishanth Menon0192f892016-10-14 01:13:34 +00001/*
2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +00007#ifndef PLATFORM_DEF_H
8#define PLATFORM_DEF_H
Nishanth Menon0192f892016-10-14 01:13:34 +00009
10#include <arch.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011#include <plat/common/common_def.h>
12
Nishanth Menon0192f892016-10-14 01:13:34 +000013#include <board_def.h>
Nishanth Menon0192f892016-10-14 01:13:34 +000014
15/*******************************************************************************
16 * Generic platform constants
17 ******************************************************************************/
18
19/* Size of cacheable stack */
20#if IMAGE_BL31
21#define PLATFORM_STACK_SIZE 0x800
22#else
23#define PLATFORM_STACK_SIZE 0x1000
24#endif
25
Benjamin Fairf807a342016-10-18 14:32:06 -050026#define PLATFORM_SYSTEM_COUNT 1
27#define PLATFORM_CORE_COUNT (K3_CLUSTER0_CORE_COUNT + \
28 K3_CLUSTER1_CORE_COUNT + \
29 K3_CLUSTER2_CORE_COUNT + \
30 K3_CLUSTER3_CORE_COUNT)
31
Andrew F. Davisb208ae32019-03-27 09:37:10 -050032#define PLATFORM_CLUSTER_COUNT ((K3_CLUSTER0_CORE_COUNT != 0) + \
33 (K3_CLUSTER1_CORE_COUNT != 0) + \
34 (K3_CLUSTER2_CORE_COUNT != 0) + \
35 (K3_CLUSTER3_CORE_COUNT != 0))
Benjamin Fairf807a342016-10-18 14:32:06 -050036
Andrew F. Davis34d8b682018-06-25 12:10:53 -050037#define PLAT_NUM_PWR_DOMAINS (PLATFORM_SYSTEM_COUNT + \
38 PLATFORM_CLUSTER_COUNT + \
Nishanth Menon0192f892016-10-14 01:13:34 +000039 PLATFORM_CORE_COUNT)
Andrew F. Davis34d8b682018-06-25 12:10:53 -050040#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
Andrew Davis49dd30c2022-11-11 12:49:38 -060041#define PLAT_MAX_OFF_STATE U(2)
42#define PLAT_MAX_RET_STATE U(1)
Nishanth Menon0192f892016-10-14 01:13:34 +000043
44/*******************************************************************************
45 * Memory layout constants
46 ******************************************************************************/
47
48/*
Andrew Davis49dd30c2022-11-11 12:49:38 -060049 * This RAM will be used for the bootloader including code, bss, and stacks.
50 * It may need to be increased if BL31 grows in size.
Andrew F. Davis9b9ac452019-01-22 14:00:16 -060051 *
Andrew Davis49dd30c2022-11-11 12:49:38 -060052 * The link addresses are determined by BL31_BASE + offset.
53 * When ENABLE_PIE is set, the TF images can be loaded anywhere, so
54 * BL31_BASE is really arbitrary.
Nishanth Menon0192f892016-10-14 01:13:34 +000055 *
Andrew Davis49dd30c2022-11-11 12:49:38 -060056 * When ENABLE_PIE is unset, BL31_BASE should be chosen so that
57 * it matches to the physical address where BL31 is loaded, that is,
58 * BL31_BASE should be the base address of the RAM region.
59 *
60 * Lets make things explicit by mapping BL31_BASE to 0x0 since ENABLE_PIE is
61 * defined as default for our platform.
Nishanth Menon0192f892016-10-14 01:13:34 +000062 */
Andrew Davis49dd30c2022-11-11 12:49:38 -060063#define BL31_BASE UL(0x00000000) /* PIE remapped on fly */
64#define BL31_SIZE UL(0x00020000) /* 128k */
65#define BL31_LIMIT (BL31_BASE + BL31_SIZE)
Nishanth Menon0192f892016-10-14 01:13:34 +000066
67/*
Nishanth Menon3ed1b282016-10-14 01:13:45 +000068 * Defines the maximum number of translation tables that are allocated by the
69 * translation table library code. To minimize the amount of runtime memory
70 * used, choose the smallest value needed to map the required virtual addresses
71 * for each BL stage.
72 */
Nishanth Menon3a9ba662021-03-26 00:34:17 -050073#if USE_COHERENT_MEM
74#define MAX_XLAT_TABLES 10
75#else
76#define MAX_XLAT_TABLES 9
77#endif
Nishanth Menon3ed1b282016-10-14 01:13:45 +000078
79/*
80 * Defines the maximum number of regions that are allocated by the translation
81 * table library code. A region consists of physical base address, virtual base
82 * address, size and attributes (Device/Memory, RO/RW, Secure/Non-Secure), as
83 * defined in the `mmap_region_t` structure. The platform defines the regions
84 * that should be mapped. Then, the translation table library will create the
85 * corresponding tables and descriptors at runtime. To minimize the amount of
86 * runtime memory used, choose the smallest value needed to register the
87 * required regions for each BL stage.
88 */
Andrew F. Davis537d3ff2018-05-04 19:06:08 +000089#define MAX_MMAP_REGIONS 11
Nishanth Menon3ed1b282016-10-14 01:13:45 +000090
91/*
92 * Defines the total size of the address space in bytes. For example, for a 32
93 * bit address space, this value should be `(1ull << 32)`.
94 */
95#define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32)
96#define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32)
97
98/*
Nishanth Menon0192f892016-10-14 01:13:34 +000099 * Some data must be aligned on the biggest cache line size in the platform.
100 * This is known only to the platform as it might have a combination of
101 * integrated and external caches.
102 */
103#define CACHE_WRITEBACK_SHIFT 6
104#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
105
Nishanth Menonce976042016-10-14 01:13:44 +0000106/* Platform default console definitions */
Andrew F. Davis42c277b2019-01-22 13:36:48 -0600107#ifndef K3_USART_BASE
Jan Kiszkab99c0782020-05-20 07:35:48 +0200108#define K3_USART_BASE (0x02800000 + 0x10000 * K3_USART)
Nishanth Menonce976042016-10-14 01:13:44 +0000109#endif
110
111/* USART has a default size for address space */
112#define K3_USART_SIZE 0x1000
113
114#ifndef K3_USART_CLK_SPEED
115#define K3_USART_CLK_SPEED 48000000
116#endif
117
Nishanth Menonce976042016-10-14 01:13:44 +0000118/* Crash console defaults */
Andrew F. Davis42c277b2019-01-22 13:36:48 -0600119#define CRASH_CONSOLE_BASE K3_USART_BASE
Nishanth Menonce976042016-10-14 01:13:44 +0000120#define CRASH_CONSOLE_CLK K3_USART_CLK_SPEED
121#define CRASH_CONSOLE_BAUD_RATE K3_USART_BAUD
122
Nishanth Menon1f0b51b2016-10-14 01:13:48 +0000123/* Timer frequency */
124#ifndef SYS_COUNTER_FREQ_IN_TICKS
125#define SYS_COUNTER_FREQ_IN_TICKS 200000000
126#endif
127
Nishanth Menonf97ad372016-10-14 01:13:49 +0000128/* Interrupt numbers */
129#define ARM_IRQ_SEC_PHY_TIMER 29
130
131#define ARM_IRQ_SEC_SGI_0 8
132#define ARM_IRQ_SEC_SGI_1 9
133#define ARM_IRQ_SEC_SGI_2 10
134#define ARM_IRQ_SEC_SGI_3 11
135#define ARM_IRQ_SEC_SGI_4 12
136#define ARM_IRQ_SEC_SGI_5 13
137#define ARM_IRQ_SEC_SGI_6 14
138#define ARM_IRQ_SEC_SGI_7 15
139
140/*
141 * Define properties of Group 1 Secure and Group 0 interrupts as per GICv3
142 * terminology. On a GICv2 system or mode, the lists will be merged and treated
143 * as Group 0 interrupts.
144 */
145#define PLAT_ARM_G1S_IRQ_PROPS(grp) \
146 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
147 GIC_INTR_CFG_LEVEL), \
148 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \
149 GIC_INTR_CFG_EDGE), \
150 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \
151 GIC_INTR_CFG_EDGE), \
152 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \
153 GIC_INTR_CFG_EDGE), \
154 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \
155 GIC_INTR_CFG_EDGE), \
156 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \
157 GIC_INTR_CFG_EDGE), \
158 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \
159 GIC_INTR_CFG_EDGE)
160
161#define PLAT_ARM_G0_IRQ_PROPS(grp) \
162 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \
163 GIC_INTR_CFG_EDGE), \
164 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \
165 GIC_INTR_CFG_EDGE)
166
Nishanth Menon651ff1a2020-12-10 20:51:51 -0600167
168#define K3_GTC_BASE 0x00A90000
169/* We just need 20 byte offset, but simpler to just remap the 64K page in */
170#define K3_GTC_SIZE 0x10000
171#define K3_GTC_CNTCR_OFFSET 0x00
172#define K3_GTC_CNTCR_EN_MASK 0x01
173#define K3_GTC_CNTCR_HDBG_MASK 0x02
174#define K3_GTC_CNTFID0_OFFSET 0x20
175
Andrew F. Davis75ad53f2019-01-22 12:39:31 -0600176#define K3_GIC_BASE 0x01800000
177#define K3_GIC_SIZE 0x200000
Nishanth Menonf97ad372016-10-14 01:13:49 +0000178
Nishanth Menond32de842020-12-10 18:39:41 -0600179#if !K3_SEC_PROXY_LITE
Andrew F. Davis537d3ff2018-05-04 19:06:08 +0000180#define SEC_PROXY_DATA_BASE 0x32C00000
181#define SEC_PROXY_DATA_SIZE 0x80000
182#define SEC_PROXY_SCFG_BASE 0x32800000
183#define SEC_PROXY_SCFG_SIZE 0x80000
184#define SEC_PROXY_RT_BASE 0x32400000
185#define SEC_PROXY_RT_SIZE 0x80000
Nishanth Menond32de842020-12-10 18:39:41 -0600186#else
187#define SEC_PROXY_DATA_BASE 0x4D000000
188#define SEC_PROXY_DATA_SIZE 0x80000
189#define SEC_PROXY_SCFG_BASE 0x4A400000
190#define SEC_PROXY_SCFG_SIZE 0x80000
191#define SEC_PROXY_RT_BASE 0x4A600000
192#define SEC_PROXY_RT_SIZE 0x80000
193#endif /* K3_SEC_PROXY_LITE */
Andrew F. Davis537d3ff2018-05-04 19:06:08 +0000194
195#define SEC_PROXY_TIMEOUT_US 1000000
196#define SEC_PROXY_MAX_MESSAGE_SIZE 56
197
Andrew F. Davisa513b2a2018-05-04 19:06:09 +0000198#define TI_SCI_HOST_ID 10
199#define TI_SCI_MAX_MESSAGE_SIZE 52
200
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000201#endif /* PLATFORM_DEF_H */