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tony.xie54973e72017-04-24 16:18:10 +08001/*
2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
3 *
dp-armd91aaae2017-05-10 15:16:15 +01004 * SPDX-License-Identifier: BSD-3-Clause
tony.xie54973e72017-04-24 16:18:10 +08005 */
6
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +00007#ifndef SOC_H
8#define SOC_H
tony.xie54973e72017-04-24 16:18:10 +08009
10/******************************* stimer ***************************************/
11#define TIMER_LOADE_COUNT0 0x00
12#define TIMER_LOADE_COUNT1 0x04
13#define TIMER_CURRENT_VALUE0 0x08
14#define TIMER_CURRENT_VALUE1 0x0C
15#define TIMER_CONTROL_REG 0x10
16#define TIMER_INTSTATUS 0x18
17#define TIMER_EN 0x1
18
tony.xie54973e72017-04-24 16:18:10 +080019/**************************** read/write **************************************/
20#ifndef BITS_WMSK
21#define BITS_WMSK(msk, shift) ((msk) << (shift + REG_MSK_SHIFT))
22#endif
23
24/**************************** cru *********************************************/
25enum plls_id {
26 APLL_ID = 0,
27 DPLL_ID,
28 CPLL_ID,
29 GPLL_ID,
Elyes Haouas2be03c02023-02-13 09:14:48 +010030 RESERVE,
tony.xie54973e72017-04-24 16:18:10 +080031 NPLL_ID,
32 MAX_PLL,
33};
34
35#define CRU_CRU_MODE 0x0080
36#define CRU_CRU_MISC 0x0084
37#define CRU_GLB_SRST_FST 0x009c
38#define CRU_GLB_SRST_FST_VALUE 0xfdb9
39#define PLL_CONS(id, i) (0x020 * (id) + ((i) * 4))
40#define CRU_CLKSEL_CON(i) (0x100 + ((i) * 4))
41#define CRU_CLKSEL_NUMS 53
42#define CRU_CLKGATE_CON(i) (0x200 + ((i) * 4))
43#define CRU_CLKGATE_NUMS 29
44#define CRU_SOFTRSTS_CON(n) (0x300 + ((n) * 4))
45#define CRU_SOFTRSTS_NUMS 12
46#define CRU_PLL_CON_NUMS 5
47
48/* PLLn_CON1 */
49#define PLL_IS_LOCKED BIT(10)
50/* PLLn_CON0 */
51#define PLL_BYPASS BITS_WITH_WMASK(1, 0x1, 15)
52#define PLL_NO_BYPASS BITS_WITH_WMASK(0, 0x1, 15)
53/* CRU_MODE */
54#define PLL_SLOW_MODE(id) ((id) == NPLL_ID) ? \
55 BITS_WITH_WMASK(0, 0x1, 1) : \
56 BITS_WITH_WMASK(0, 0x1, ((id) * 4))
57#define PLL_NORM_MODE(id) ((id) == NPLL_ID) ? \
58 BITS_WITH_WMASK(1, 0x1, 1) : \
59 BITS_WITH_WMASK(1, 0x1, ((id) * 4))
60
61#define CRU_GATEID_CONS(ID) (0x200 + (ID / 16) * 4)
62#define CRU_CONS_GATEID(i) (16 * (i))
63#define GATE_ID(reg, bit) ((reg * 16) + bit)
64
65#define PLL_LOCKED_TIMEOUT 600000U
66
67#define STIMER_CHN_BASE(n) (STIME_BASE + 0x20 * (n))
68/************************** config regs ***************************************/
69#define FIREWALL_CFG_FW_SYS_CON(n) (0x000 + (n) * 4)
70#define FIREWALL_DDR_FW_DDR_RGN(n) (0x000 + (n) * 4)
71#define FIREWALL_DDR_FW_DDR_MST(n) (0x020 + (n) * 4)
72#define FIREWALL_DDR_FW_DDR_CON_REG (0x040)
73#define GRF_SOC_CON(n) (0x400 + (n) * 4)
74#define GRF_SOC_STATUS(n) (0x480 + (n) * 4)
75#define GRF_CPU_STATUS(n) (0x520 + (n) * 4)
76#define GRF_OS_REG(n) (0x5c8 + (n) * 4)
77#define DDRGRF_SOC_CON(n) (0x000 + (n) * 4)
78#define DDRGRF_SOC_STATUS(n) (0x100 + (n) * 4)
79#define SGRF_SOC_CON(n) (0x000 + (n) * 4)
80#define SGRF_DMAC_CON(n) (0x100 + (n) * 4)
81#define SGRF_HDCP_KEY_CON(n) (0x280 + (n) * 4)
82
83#define DDR_PCTL2_PWRCTL 0x30
84/************************** regs func *****************************************/
85#define STIMER_S BIT(23)
86#define SGRF_SLV_S_ALL_NS 0x0
87#define SGRF_MST_S_ALL_NS 0xffffffff
88#define DMA_IRQ_BOOT_NS 0xffffffff
89#define DMA_MANAGER_BOOT_NS 0x80008000
90#define DMA_PERI_CH_NS_15_0 0xffffffff
91#define DMA_PERI_CH_NS_19_16 0x000f000f
92#define DMA_SOFTRST_REQ 0x01000100
93#define DMA_SOFTRST_RLS 0x01000000
94
95#define SELFREF_EN BIT(0)
96/************************** cpu ***********************************************/
97#define CPU_BOOT_ADDR_WMASK 0xffff0000
98#define CPU_BOOT_ADDR_ALIGN 16
99
100/************************** ddr secure region *********************************/
101#define PLAT_MAX_DDR_CAPACITY_MB 4096
102#define RG_MAP_SECURE(top, base) ((((top) - 1) << 16) | (base))
103
104/************************** gpio2_d2 ******************************************/
105#define SWPORTA_DR 0x00
106#define SWPORTA_DDR 0x04
107#define GPIO2_D2 BIT(26)
108#define GPIO2_D2_GPIO_MODE 0x30
109#define GRF_GPIO2D_IOMUX 0x34
110
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000111#endif /* SOC_H */