blob: a1f35b2826e600cee3a9b44e8557352bd9aa91b6 [file] [log] [blame]
tony.xie54973e72017-04-24 16:18:10 +08001/*
2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
3 *
dp-armd91aaae2017-05-10 15:16:15 +01004 * SPDX-License-Identifier: BSD-3-Clause
tony.xie54973e72017-04-24 16:18:10 +08005 */
6
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +00007#ifndef SOC_H
8#define SOC_H
tony.xie54973e72017-04-24 16:18:10 +08009
10/******************************* stimer ***************************************/
11#define TIMER_LOADE_COUNT0 0x00
12#define TIMER_LOADE_COUNT1 0x04
13#define TIMER_CURRENT_VALUE0 0x08
14#define TIMER_CURRENT_VALUE1 0x0C
15#define TIMER_CONTROL_REG 0x10
16#define TIMER_INTSTATUS 0x18
17#define TIMER_EN 0x1
18
19extern const unsigned char rockchip_power_domain_tree_desc[];
20
21/**************************** read/write **************************************/
22#ifndef BITS_WMSK
23#define BITS_WMSK(msk, shift) ((msk) << (shift + REG_MSK_SHIFT))
24#endif
25
26/**************************** cru *********************************************/
27enum plls_id {
28 APLL_ID = 0,
29 DPLL_ID,
30 CPLL_ID,
31 GPLL_ID,
32 REVERVE,
33 NPLL_ID,
34 MAX_PLL,
35};
36
37#define CRU_CRU_MODE 0x0080
38#define CRU_CRU_MISC 0x0084
39#define CRU_GLB_SRST_FST 0x009c
40#define CRU_GLB_SRST_FST_VALUE 0xfdb9
41#define PLL_CONS(id, i) (0x020 * (id) + ((i) * 4))
42#define CRU_CLKSEL_CON(i) (0x100 + ((i) * 4))
43#define CRU_CLKSEL_NUMS 53
44#define CRU_CLKGATE_CON(i) (0x200 + ((i) * 4))
45#define CRU_CLKGATE_NUMS 29
46#define CRU_SOFTRSTS_CON(n) (0x300 + ((n) * 4))
47#define CRU_SOFTRSTS_NUMS 12
48#define CRU_PLL_CON_NUMS 5
49
50/* PLLn_CON1 */
51#define PLL_IS_LOCKED BIT(10)
52/* PLLn_CON0 */
53#define PLL_BYPASS BITS_WITH_WMASK(1, 0x1, 15)
54#define PLL_NO_BYPASS BITS_WITH_WMASK(0, 0x1, 15)
55/* CRU_MODE */
56#define PLL_SLOW_MODE(id) ((id) == NPLL_ID) ? \
57 BITS_WITH_WMASK(0, 0x1, 1) : \
58 BITS_WITH_WMASK(0, 0x1, ((id) * 4))
59#define PLL_NORM_MODE(id) ((id) == NPLL_ID) ? \
60 BITS_WITH_WMASK(1, 0x1, 1) : \
61 BITS_WITH_WMASK(1, 0x1, ((id) * 4))
62
63#define CRU_GATEID_CONS(ID) (0x200 + (ID / 16) * 4)
64#define CRU_CONS_GATEID(i) (16 * (i))
65#define GATE_ID(reg, bit) ((reg * 16) + bit)
66
67#define PLL_LOCKED_TIMEOUT 600000U
68
69#define STIMER_CHN_BASE(n) (STIME_BASE + 0x20 * (n))
70/************************** config regs ***************************************/
71#define FIREWALL_CFG_FW_SYS_CON(n) (0x000 + (n) * 4)
72#define FIREWALL_DDR_FW_DDR_RGN(n) (0x000 + (n) * 4)
73#define FIREWALL_DDR_FW_DDR_MST(n) (0x020 + (n) * 4)
74#define FIREWALL_DDR_FW_DDR_CON_REG (0x040)
75#define GRF_SOC_CON(n) (0x400 + (n) * 4)
76#define GRF_SOC_STATUS(n) (0x480 + (n) * 4)
77#define GRF_CPU_STATUS(n) (0x520 + (n) * 4)
78#define GRF_OS_REG(n) (0x5c8 + (n) * 4)
79#define DDRGRF_SOC_CON(n) (0x000 + (n) * 4)
80#define DDRGRF_SOC_STATUS(n) (0x100 + (n) * 4)
81#define SGRF_SOC_CON(n) (0x000 + (n) * 4)
82#define SGRF_DMAC_CON(n) (0x100 + (n) * 4)
83#define SGRF_HDCP_KEY_CON(n) (0x280 + (n) * 4)
84
85#define DDR_PCTL2_PWRCTL 0x30
86/************************** regs func *****************************************/
87#define STIMER_S BIT(23)
88#define SGRF_SLV_S_ALL_NS 0x0
89#define SGRF_MST_S_ALL_NS 0xffffffff
90#define DMA_IRQ_BOOT_NS 0xffffffff
91#define DMA_MANAGER_BOOT_NS 0x80008000
92#define DMA_PERI_CH_NS_15_0 0xffffffff
93#define DMA_PERI_CH_NS_19_16 0x000f000f
94#define DMA_SOFTRST_REQ 0x01000100
95#define DMA_SOFTRST_RLS 0x01000000
96
97#define SELFREF_EN BIT(0)
98/************************** cpu ***********************************************/
99#define CPU_BOOT_ADDR_WMASK 0xffff0000
100#define CPU_BOOT_ADDR_ALIGN 16
101
102/************************** ddr secure region *********************************/
103#define PLAT_MAX_DDR_CAPACITY_MB 4096
104#define RG_MAP_SECURE(top, base) ((((top) - 1) << 16) | (base))
105
106/************************** gpio2_d2 ******************************************/
107#define SWPORTA_DR 0x00
108#define SWPORTA_DDR 0x04
109#define GPIO2_D2 BIT(26)
110#define GPIO2_D2_GPIO_MODE 0x30
111#define GRF_GPIO2D_IOMUX 0x34
112
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000113#endif /* SOC_H */