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Dan Handley9df48042015-03-19 18:58:55 +00001/*
Pranav Madhue3173282022-07-27 12:49:24 +05302 * Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Dan Handley9df48042015-03-19 18:58:55 +00005 */
6
Soby Mathewfeac8fc2015-09-29 15:47:16 +01007#include <assert.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00008
Dan Handley9df48042015-03-19 18:58:55 +00009#include <platform_def.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010
11#include <arch_helpers.h>
Pranav Madhue3173282022-07-27 12:49:24 +053012#include <bl31/interrupt_mgmt.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000013#include <common/debug.h>
Antonio Nino Diaz326f56b2019-01-23 18:55:03 +000014#include <drivers/arm/css/css_scp.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000015#include <lib/cassert.h>
Antonio Nino Diazbd7b7402019-01-25 14:30:04 +000016#include <plat/arm/common/plat_arm.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000017
Pranav Madhue3173282022-07-27 12:49:24 +053018#include <plat/common/platform.h>
19
Pranav Madhu9ad55b02022-07-27 13:12:27 +053020#include <plat/arm/css/common/css_pm.h>
21
Soby Mathewfeac8fc2015-09-29 15:47:16 +010022/* Allow CSS platforms to override `plat_arm_psci_pm_ops` */
23#pragma weak plat_arm_psci_pm_ops
Soby Mathewfec4eb72015-07-01 16:16:20 +010024
Soby Mathew7799cf72015-04-16 14:49:09 +010025#if ARM_RECOM_STATE_ID_ENC
26/*
27 * The table storing the valid idle power states. Ensure that the
28 * array entries are populated in ascending order of state-id to
29 * enable us to use binary search during power state validation.
30 * The table must be terminated by a NULL entry.
31 */
32const unsigned int arm_pm_idle_states[] = {
Soby Mathewa869de12015-05-08 10:18:59 +010033 /* State-id - 0x001 */
34 arm_make_pwrstate_lvl2(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_RUN,
35 ARM_LOCAL_STATE_RET, ARM_PWR_LVL0, PSTATE_TYPE_STANDBY),
36 /* State-id - 0x002 */
37 arm_make_pwrstate_lvl2(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_RUN,
38 ARM_LOCAL_STATE_OFF, ARM_PWR_LVL0, PSTATE_TYPE_POWERDOWN),
39 /* State-id - 0x022 */
40 arm_make_pwrstate_lvl2(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_OFF,
41 ARM_LOCAL_STATE_OFF, ARM_PWR_LVL1, PSTATE_TYPE_POWERDOWN),
42#if PLAT_MAX_PWR_LVL > ARM_PWR_LVL1
43 /* State-id - 0x222 */
44 arm_make_pwrstate_lvl2(ARM_LOCAL_STATE_OFF, ARM_LOCAL_STATE_OFF,
45 ARM_LOCAL_STATE_OFF, ARM_PWR_LVL2, PSTATE_TYPE_POWERDOWN),
46#endif
Soby Mathew7799cf72015-04-16 14:49:09 +010047 0,
48};
Soby Mathewa869de12015-05-08 10:18:59 +010049#endif /* __ARM_RECOM_STATE_ID_ENC__ */
Soby Mathew7799cf72015-04-16 14:49:09 +010050
Soby Mathew61e8d0b2015-10-12 17:32:29 +010051/*
52 * All the power management helpers in this file assume at least cluster power
53 * level is supported.
54 */
55CASSERT(PLAT_MAX_PWR_LVL >= ARM_PWR_LVL1,
56 assert_max_pwr_lvl_supported_mismatch);
57
Soby Mathew7a3b5eb2016-12-09 15:23:08 +000058/*
59 * Ensure that the PLAT_MAX_PWR_LVL is not greater than CSS_SYSTEM_PWR_DMN_LVL
60 * assumed by the CSS layer.
61 */
62CASSERT(PLAT_MAX_PWR_LVL <= CSS_SYSTEM_PWR_DMN_LVL,
63 assert_max_pwr_lvl_higher_than_css_sys_lvl);
64
Dan Handley9df48042015-03-19 18:58:55 +000065/*******************************************************************************
Soby Mathewfec4eb72015-07-01 16:16:20 +010066 * Handler called when a power domain is about to be turned on. The
Dan Handley9df48042015-03-19 18:58:55 +000067 * level and mpidr determine the affinity instance.
68 ******************************************************************************/
Soby Mathewfec4eb72015-07-01 16:16:20 +010069int css_pwr_domain_on(u_register_t mpidr)
Dan Handley9df48042015-03-19 18:58:55 +000070{
Soby Mathew200fffd2016-10-21 11:34:59 +010071 css_scp_on(mpidr);
Dan Handley9df48042015-03-19 18:58:55 +000072
73 return PSCI_E_SUCCESS;
74}
75
Soby Mathew12012dd2015-10-26 14:01:53 +000076static void css_pwr_domain_on_finisher_common(
77 const psci_power_state_t *target_state)
Dan Handley9df48042015-03-19 18:58:55 +000078{
Soby Mathew12012dd2015-10-26 14:01:53 +000079 assert(CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF);
Soby Mathew61e8d0b2015-10-12 17:32:29 +010080
Dan Handley9df48042015-03-19 18:58:55 +000081 /*
82 * Perform the common cluster specific operations i.e enable coherency
83 * if this cluster was off.
84 */
Soby Mathew12012dd2015-10-26 14:01:53 +000085 if (CSS_CLUSTER_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF)
Vikram Kanigirifbb13012016-02-15 11:54:14 +000086 plat_arm_interconnect_enter_coherency();
Soby Mathew12012dd2015-10-26 14:01:53 +000087}
Dan Handley9df48042015-03-19 18:58:55 +000088
Soby Mathew12012dd2015-10-26 14:01:53 +000089/*******************************************************************************
90 * Handler called when a power level has just been powered on after
91 * being turned off earlier. The target_state encodes the low power state that
92 * each level has woken up from. This handler would never be invoked with
93 * the system power domain uninitialized as either the primary would have taken
94 * care of it as part of cold boot or the first core awakened from system
95 * suspend would have already initialized it.
96 ******************************************************************************/
97void css_pwr_domain_on_finish(const psci_power_state_t *target_state)
98{
99 /* Assert that the system power domain need not be initialized */
Nariman Poushincd956262018-05-01 09:28:40 +0100100 assert(css_system_pwr_state(target_state) == ARM_LOCAL_STATE_RUN);
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100101
Madhukar Pappireddy2859b7d2019-06-10 16:54:36 -0500102 css_pwr_domain_on_finisher_common(target_state);
103}
104
105/*******************************************************************************
106 * Handler called when a power domain has just been powered on and the cpu
107 * and its cluster are fully participating in coherent transaction on the
108 * interconnect. Data cache must be enabled for CPU at this point.
109 ******************************************************************************/
110void css_pwr_domain_on_finish_late(const psci_power_state_t *target_state)
111{
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000112 /* Program the gic per-cpu distributor or re-distributor interface */
113 plat_arm_gic_pcpu_init();
114
Madhukar Pappireddy2859b7d2019-06-10 16:54:36 -0500115 /* Enable the gic cpu interface */
116 plat_arm_gic_cpuif_enable();
Pranav Madhue3173282022-07-27 12:49:24 +0530117
118 /* Setup the CPU power down request interrupt for secondary core(s) */
119 css_setup_cpu_pwr_down_intr();
Dan Handley9df48042015-03-19 18:58:55 +0000120}
121
122/*******************************************************************************
123 * Common function called while turning a cpu off or suspending it. It is called
124 * from css_off() or css_suspend() when these functions in turn are called for
Soby Mathewfec4eb72015-07-01 16:16:20 +0100125 * power domain at the highest power level which will be powered down. It
126 * performs the actions common to the OFF and SUSPEND calls.
Dan Handley9df48042015-03-19 18:58:55 +0000127 ******************************************************************************/
Soby Mathewfec4eb72015-07-01 16:16:20 +0100128static void css_power_down_common(const psci_power_state_t *target_state)
Dan Handley9df48042015-03-19 18:58:55 +0000129{
Dan Handley9df48042015-03-19 18:58:55 +0000130 /* Prevent interrupts from spuriously waking up this cpu */
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000131 plat_arm_gic_cpuif_disable();
Dan Handley9df48042015-03-19 18:58:55 +0000132
133 /* Cluster is to be turned off, so disable coherency */
Madhukar Pappireddy90d65322019-10-30 14:24:39 -0500134 if (CSS_CLUSTER_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF) {
Vikram Kanigirifbb13012016-02-15 11:54:14 +0000135 plat_arm_interconnect_exit_coherency();
Madhukar Pappireddy90d65322019-10-30 14:24:39 -0500136
137#if HW_ASSISTED_COHERENCY
138 uint32_t reg;
139
140 /*
141 * If we have determined this core to be the last man standing and we
142 * intend to power down the cluster proactively, we provide a hint to
143 * the power controller that cluster power is not required when all
144 * cores are powered down.
145 * Note that this is only an advisory to power controller and is supported
146 * by SoCs with DynamIQ Shared Units only.
147 */
148 reg = read_clusterpwrdn();
149
150 /* Clear and set bit 0 : Cluster power not required */
151 reg &= ~DSU_CLUSTER_PWR_MASK;
152 reg |= DSU_CLUSTER_PWR_OFF;
153 write_clusterpwrdn(reg);
154#endif
155 }
Dan Handley9df48042015-03-19 18:58:55 +0000156}
157
158/*******************************************************************************
Soby Mathewfec4eb72015-07-01 16:16:20 +0100159 * Handler called when a power domain is about to be turned off. The
160 * target_state encodes the power state that each level should transition to.
Dan Handley9df48042015-03-19 18:58:55 +0000161 ******************************************************************************/
Soby Mathewfeac8fc2015-09-29 15:47:16 +0100162void css_pwr_domain_off(const psci_power_state_t *target_state)
Dan Handley9df48042015-03-19 18:58:55 +0000163{
Soby Mathew12012dd2015-10-26 14:01:53 +0000164 assert(CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF);
Soby Mathewfec4eb72015-07-01 16:16:20 +0100165 css_power_down_common(target_state);
Soby Mathew200fffd2016-10-21 11:34:59 +0100166 css_scp_off(target_state);
Dan Handley9df48042015-03-19 18:58:55 +0000167}
168
169/*******************************************************************************
Soby Mathewfec4eb72015-07-01 16:16:20 +0100170 * Handler called when a power domain is about to be suspended. The
171 * target_state encodes the power state that each level should transition to.
Dan Handley9df48042015-03-19 18:58:55 +0000172 ******************************************************************************/
Soby Mathewfeac8fc2015-09-29 15:47:16 +0100173void css_pwr_domain_suspend(const psci_power_state_t *target_state)
Dan Handley9df48042015-03-19 18:58:55 +0000174{
Soby Mathewfec4eb72015-07-01 16:16:20 +0100175 /*
Soby Mathew12012dd2015-10-26 14:01:53 +0000176 * CSS currently supports retention only at cpu level. Just return
Soby Mathewfec4eb72015-07-01 16:16:20 +0100177 * as nothing is to be done for retention.
178 */
Soby Mathew12012dd2015-10-26 14:01:53 +0000179 if (CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_RET)
Dan Handley9df48042015-03-19 18:58:55 +0000180 return;
181
Soby Mathew9ca28062017-10-11 16:08:58 +0100182
Soby Mathew12012dd2015-10-26 14:01:53 +0000183 assert(CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF);
Soby Mathewfec4eb72015-07-01 16:16:20 +0100184 css_power_down_common(target_state);
Soby Mathew9ca28062017-10-11 16:08:58 +0100185
186 /* Perform system domain state saving if issuing system suspend */
Nariman Poushincd956262018-05-01 09:28:40 +0100187 if (css_system_pwr_state(target_state) == ARM_LOCAL_STATE_OFF) {
Soby Mathew9ca28062017-10-11 16:08:58 +0100188 arm_system_pwr_domain_save();
189
190 /* Power off the Redistributor after having saved its context */
191 plat_arm_gic_redistif_off();
192 }
193
Soby Mathew200fffd2016-10-21 11:34:59 +0100194 css_scp_suspend(target_state);
Dan Handley9df48042015-03-19 18:58:55 +0000195}
196
197/*******************************************************************************
Soby Mathewfec4eb72015-07-01 16:16:20 +0100198 * Handler called when a power domain has just been powered on after
199 * having been suspended earlier. The target_state encodes the low power state
200 * that each level has woken up from.
Dan Handley9df48042015-03-19 18:58:55 +0000201 * TODO: At the moment we reuse the on finisher and reinitialize the secure
202 * context. Need to implement a separate suspend finisher.
203 ******************************************************************************/
Soby Mathewfeac8fc2015-09-29 15:47:16 +0100204void css_pwr_domain_suspend_finish(
Soby Mathewfec4eb72015-07-01 16:16:20 +0100205 const psci_power_state_t *target_state)
Dan Handley9df48042015-03-19 18:58:55 +0000206{
Soby Mathew12012dd2015-10-26 14:01:53 +0000207 /* Return as nothing is to be done on waking up from retention. */
208 if (CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_RET)
Soby Mathewfec4eb72015-07-01 16:16:20 +0100209 return;
210
Soby Mathew12012dd2015-10-26 14:01:53 +0000211 /* Perform system domain restore if woken up from system suspend */
Nariman Poushincd956262018-05-01 09:28:40 +0100212 if (css_system_pwr_state(target_state) == ARM_LOCAL_STATE_OFF)
Soby Mathew9ca28062017-10-11 16:08:58 +0100213 /*
214 * At this point, the Distributor must be powered on to be ready
215 * to have its state restored. The Redistributor will be powered
216 * on as part of gicv3_rdistif_init_restore.
217 */
Soby Mathew12012dd2015-10-26 14:01:53 +0000218 arm_system_pwr_domain_resume();
Soby Mathew12012dd2015-10-26 14:01:53 +0000219
220 css_pwr_domain_on_finisher_common(target_state);
Madhukar Pappireddy2859b7d2019-06-10 16:54:36 -0500221
222 /* Enable the gic cpu interface */
223 plat_arm_gic_cpuif_enable();
Dan Handley9df48042015-03-19 18:58:55 +0000224}
225
226/*******************************************************************************
227 * Handlers to shutdown/reboot the system
228 ******************************************************************************/
Soby Mathewfeac8fc2015-09-29 15:47:16 +0100229void __dead2 css_system_off(void)
Dan Handley9df48042015-03-19 18:58:55 +0000230{
Soby Mathew200fffd2016-10-21 11:34:59 +0100231 css_scp_sys_shutdown();
Dan Handley9df48042015-03-19 18:58:55 +0000232}
233
Soby Mathewfeac8fc2015-09-29 15:47:16 +0100234void __dead2 css_system_reset(void)
Dan Handley9df48042015-03-19 18:58:55 +0000235{
Soby Mathew200fffd2016-10-21 11:34:59 +0100236 css_scp_sys_reboot();
Dan Handley9df48042015-03-19 18:58:55 +0000237}
238
239/*******************************************************************************
Soby Mathewfec4eb72015-07-01 16:16:20 +0100240 * Handler called when the CPU power domain is about to enter standby.
Dan Handley9df48042015-03-19 18:58:55 +0000241 ******************************************************************************/
Soby Mathewfec4eb72015-07-01 16:16:20 +0100242void css_cpu_standby(plat_local_state_t cpu_state)
Dan Handley9df48042015-03-19 18:58:55 +0000243{
244 unsigned int scr;
245
Soby Mathewfec4eb72015-07-01 16:16:20 +0100246 assert(cpu_state == ARM_LOCAL_STATE_RET);
247
Dan Handley9df48042015-03-19 18:58:55 +0000248 scr = read_scr_el3();
David Wangc1d9cfb2016-06-07 09:22:40 +0800249 /*
250 * Enable the Non secure interrupt to wake the CPU.
251 * In GICv3 affinity routing mode, the non secure group1 interrupts use
252 * the PhysicalFIQ at EL3 whereas in GICv2, it uses the PhysicalIRQ.
253 * Enabling both the bits works for both GICv2 mode and GICv3 affinity
254 * routing mode.
255 */
256 write_scr_el3(scr | SCR_IRQ_BIT | SCR_FIQ_BIT);
Dan Handley9df48042015-03-19 18:58:55 +0000257 isb();
258 dsb();
259 wfi();
260
261 /*
262 * Restore SCR to the original value, synchronisation of scr_el3 is
263 * done by eret while el3_exit to save some execution cycles.
264 */
265 write_scr_el3(scr);
266}
267
268/*******************************************************************************
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100269 * Handler called to return the 'req_state' for system suspend.
270 ******************************************************************************/
271void css_get_sys_suspend_power_state(psci_power_state_t *req_state)
272{
273 unsigned int i;
274
275 /*
276 * System Suspend is supported only if the system power domain node
277 * is implemented.
278 */
Soby Mathew7a3b5eb2016-12-09 15:23:08 +0000279 assert(PLAT_MAX_PWR_LVL == CSS_SYSTEM_PWR_DMN_LVL);
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100280
281 for (i = ARM_PWR_LVL0; i <= PLAT_MAX_PWR_LVL; i++)
282 req_state->pwr_domain_state[i] = ARM_LOCAL_STATE_OFF;
283}
284
285/*******************************************************************************
Jeenu Viswambharan9cc4fc02016-08-04 09:43:15 +0100286 * Handler to query CPU/cluster power states from SCP
287 ******************************************************************************/
288int css_node_hw_state(u_register_t mpidr, unsigned int power_level)
289{
Soby Mathew200fffd2016-10-21 11:34:59 +0100290 return css_scp_get_power_state(mpidr, power_level);
Jeenu Viswambharan9cc4fc02016-08-04 09:43:15 +0100291}
292
Soby Mathew7a3b5eb2016-12-09 15:23:08 +0000293/*
294 * The system power domain suspend is only supported only via
295 * PSCI SYSTEM_SUSPEND API. PSCI CPU_SUSPEND request to system power domain
296 * will be downgraded to the lower level.
297 */
298static int css_validate_power_state(unsigned int power_state,
299 psci_power_state_t *req_state)
300{
301 int rc;
302 rc = arm_validate_power_state(power_state, req_state);
303
304 /*
Nariman Poushin16b41092018-05-01 13:07:47 +0100305 * Ensure that we don't overrun the pwr_domain_state array in the case
306 * where the platform supported max power level is less than the system
307 * power level
308 */
309
310#if (PLAT_MAX_PWR_LVL == CSS_SYSTEM_PWR_DMN_LVL)
311
312 /*
Soby Mathew7a3b5eb2016-12-09 15:23:08 +0000313 * Ensure that the system power domain level is never suspended
314 * via PSCI CPU SUSPEND API. Currently system suspend is only
315 * supported via PSCI SYSTEM SUSPEND API.
316 */
Nariman Poushin16b41092018-05-01 13:07:47 +0100317
318 req_state->pwr_domain_state[CSS_SYSTEM_PWR_DMN_LVL] =
319 ARM_LOCAL_STATE_RUN;
320#endif
321
Soby Mathew7a3b5eb2016-12-09 15:23:08 +0000322 return rc;
323}
324
325/*
326 * Custom `translate_power_state_by_mpidr` handler for CSS. Unlike in the
327 * `css_validate_power_state`, we do not downgrade the system power
328 * domain level request in `power_state` as it will be used to query the
329 * PSCI_STAT_COUNT/RESIDENCY at the system power domain level.
330 */
331static int css_translate_power_state_by_mpidr(u_register_t mpidr,
332 unsigned int power_state,
333 psci_power_state_t *output_state)
334{
335 return arm_validate_power_state(power_state, output_state);
336}
337
Pranav Madhue3173282022-07-27 12:49:24 +0530338/*
339 * Setup the SGI interrupt that will be used trigger the execution of power
340 * down sequence for all the secondary cores. This interrupt is setup to be
341 * handled in EL3 context at a priority defined by the platform.
342 */
343void css_setup_cpu_pwr_down_intr(void)
344{
345#if CSS_SYSTEM_GRACEFUL_RESET
346 plat_ic_set_interrupt_type(CSS_CPU_PWR_DOWN_REQ_INTR, INTR_TYPE_EL3);
347 plat_ic_set_interrupt_priority(CSS_CPU_PWR_DOWN_REQ_INTR,
348 PLAT_REBOOT_PRI);
349 plat_ic_enable_interrupt(CSS_CPU_PWR_DOWN_REQ_INTR);
350#endif
351}
352
Pranav Madhu9ad55b02022-07-27 13:12:27 +0530353/*
354 * For a graceful shutdown/reboot, each CPU in the system should do their power
355 * down sequence. On a PSCI shutdown/reboot request, only one CPU gets an
356 * opportunity to do the powerdown sequence. To achieve graceful reset, of all
357 * cores in the system, the CPU gets the opportunity raise warm reboot SGI to
358 * rest of the CPUs which are online. Add handler for the reboot SGI where the
359 * rest of the CPU execute the powerdown sequence.
360 */
361int css_reboot_interrupt_handler(uint32_t intr_raw, uint32_t flags,
362 void *handle, void *cookie)
363{
364 assert(intr_raw == CSS_CPU_PWR_DOWN_REQ_INTR);
365
366 /* Deactivate warm reboot SGI */
367 plat_ic_end_of_interrupt(CSS_CPU_PWR_DOWN_REQ_INTR);
368
369 /*
370 * Disable GIC CPU interface to prevent pending interrupt from waking
371 * up the AP from WFI.
372 */
373 plat_arm_gic_cpuif_disable();
374 plat_arm_gic_redistif_off();
375
376 psci_pwrdown_cpu(PLAT_MAX_PWR_LVL);
377
378 dmbsy();
379
380 wfi();
381 return 0;
382}
383
Jeenu Viswambharan9cc4fc02016-08-04 09:43:15 +0100384/*******************************************************************************
Soby Mathewfeac8fc2015-09-29 15:47:16 +0100385 * Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard
386 * platform will take care of registering the handlers with PSCI.
Dan Handley9df48042015-03-19 18:58:55 +0000387 ******************************************************************************/
Soby Mathew0b4c5a32016-10-21 17:51:22 +0100388plat_psci_ops_t plat_arm_psci_pm_ops = {
Soby Mathewfec4eb72015-07-01 16:16:20 +0100389 .pwr_domain_on = css_pwr_domain_on,
390 .pwr_domain_on_finish = css_pwr_domain_on_finish,
Madhukar Pappireddy2859b7d2019-06-10 16:54:36 -0500391 .pwr_domain_on_finish_late = css_pwr_domain_on_finish_late,
Soby Mathewfec4eb72015-07-01 16:16:20 +0100392 .pwr_domain_off = css_pwr_domain_off,
393 .cpu_standby = css_cpu_standby,
394 .pwr_domain_suspend = css_pwr_domain_suspend,
395 .pwr_domain_suspend_finish = css_pwr_domain_suspend_finish,
Dan Handley9df48042015-03-19 18:58:55 +0000396 .system_off = css_system_off,
397 .system_reset = css_system_reset,
Soby Mathew7a3b5eb2016-12-09 15:23:08 +0000398 .validate_power_state = css_validate_power_state,
Jeenu Viswambharan59424d82017-09-19 09:27:18 +0100399 .validate_ns_entrypoint = arm_validate_psci_entrypoint,
Soby Mathew7a3b5eb2016-12-09 15:23:08 +0000400 .translate_power_state_by_mpidr = css_translate_power_state_by_mpidr,
401 .get_node_hw_state = css_node_hw_state,
Roberto Vargasa1c16b62017-08-03 09:16:43 +0100402 .get_sys_suspend_power_state = css_get_sys_suspend_power_state,
Roberto Vargas550eb082018-01-05 16:00:05 +0000403
404#if defined(PLAT_ARM_MEM_PROT_ADDR)
Roberto Vargasa1c16b62017-08-03 09:16:43 +0100405 .mem_protect_chk = arm_psci_mem_protect_chk,
406 .read_mem_protect = arm_psci_read_mem_protect,
407 .write_mem_protect = arm_nor_psci_write_mem_protect,
408#endif
Roberto Vargas3caafd72017-08-16 08:57:45 +0100409#if CSS_USE_SCMI_SDS_DRIVER
410 .system_reset2 = css_system_reset2,
411#endif
Dan Handley9df48042015-03-19 18:58:55 +0000412};