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Yann Gautier4b0c72a2018-07-16 10:54:09 +02001/*
Yann Gautierf9d40d52019-01-17 14:41:46 +01002 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
Yann Gautier4b0c72a2018-07-16 10:54:09 +02003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef PLATFORM_DEF_H
8#define PLATFORM_DEF_H
9
10#include <arch.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011#include <drivers/arm/gic_common.h>
12#include <lib/utils_def.h>
13#include <plat/common/common_def.h>
14
Yann Gautier4b0c72a2018-07-16 10:54:09 +020015#include "../stm32mp1_def.h"
16
17/*******************************************************************************
18 * Generic platform constants
19 ******************************************************************************/
20
21/* Size of cacheable stacks */
Yann Gautier9d135e42018-07-16 19:36:06 +020022#if defined(IMAGE_BL32)
23#define PLATFORM_STACK_SIZE 0x600
24#else
Yann Gautier4b0c72a2018-07-16 10:54:09 +020025#define PLATFORM_STACK_SIZE 0xC00
Yann Gautier9d135e42018-07-16 19:36:06 +020026#endif
Yann Gautier4b0c72a2018-07-16 10:54:09 +020027
Yann Gautierb3386f72019-04-19 09:41:01 +020028#ifdef AARCH32_SP_OPTEE
29#define OPTEE_HEADER_IMAGE_NAME "teeh"
30#define OPTEE_PAGED_IMAGE_NAME "teed"
31#define OPTEE_PAGER_IMAGE_NAME "teex"
32#define OPTEE_HEADER_BINARY_TYPE U(0x20)
33#define OPTEE_PAGER_BINARY_TYPE U(0x21)
34#define OPTEE_PAGED_BINARY_TYPE U(0x22)
35#endif
36
Yann Gautier4b0c72a2018-07-16 10:54:09 +020037/* SSBL = second stage boot loader */
38#define BL33_IMAGE_NAME "ssbl"
Yann Gautier8244e1d2018-10-15 09:36:58 +020039#define BL33_BINARY_TYPE U(0x0)
Yann Gautier4b0c72a2018-07-16 10:54:09 +020040
Yann Gautiera2e2a302019-02-14 11:13:39 +010041#define STM32MP_PRIMARY_CPU U(0x0)
42#define STM32MP_SECONDARY_CPU U(0x1)
Yann Gautier4b0c72a2018-07-16 10:54:09 +020043
Deepika Bhavnani3184eea2019-12-13 10:53:12 -060044#define PLATFORM_CLUSTER_COUNT U(1)
Yann Gautier4b0c72a2018-07-16 10:54:09 +020045#define PLATFORM_CLUSTER0_CORE_COUNT U(2)
46#define PLATFORM_CLUSTER1_CORE_COUNT U(0)
47#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \
48 PLATFORM_CLUSTER0_CORE_COUNT)
49#define PLATFORM_MAX_CPUS_PER_CLUSTER 2
50
Yann Gautierf9d40d52019-01-17 14:41:46 +010051#define MAX_IO_DEVICES U(4)
52#define MAX_IO_HANDLES U(4)
53#define MAX_IO_BLOCK_DEVICES U(1)
Lionel Debieve402a46b2019-11-04 12:28:15 +010054#define MAX_IO_MTD_DEVICES U(1)
Yann Gautier4b0c72a2018-07-16 10:54:09 +020055
56/*******************************************************************************
57 * BL2 specific defines.
58 ******************************************************************************/
59/*
60 * Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug
61 * size plus a little space for growth.
62 */
Yann Gautiera2e2a302019-02-14 11:13:39 +010063#define BL2_BASE STM32MP_BL2_BASE
64#define BL2_LIMIT (STM32MP_BL2_BASE + \
65 STM32MP_BL2_SIZE)
Yann Gautier4b0c72a2018-07-16 10:54:09 +020066
67/*******************************************************************************
68 * BL32 specific defines.
69 ******************************************************************************/
Yann Gautierb3386f72019-04-19 09:41:01 +020070#ifndef AARCH32_SP_OPTEE
Yann Gautiera2e2a302019-02-14 11:13:39 +010071#define BL32_BASE STM32MP_BL32_BASE
72#define BL32_LIMIT (STM32MP_BL32_BASE + \
73 STM32MP_BL32_SIZE)
Yann Gautierb3386f72019-04-19 09:41:01 +020074#endif
Yann Gautier4b0c72a2018-07-16 10:54:09 +020075
76/*******************************************************************************
77 * BL33 specific defines.
78 ******************************************************************************/
Yann Gautiera2e2a302019-02-14 11:13:39 +010079#define BL33_BASE STM32MP_BL33_BASE
Yann Gautier4b0c72a2018-07-16 10:54:09 +020080
81/*
82 * Load address of BL33 for this platform port
83 */
Yann Gautiera2e2a302019-02-14 11:13:39 +010084#define PLAT_STM32MP_NS_IMAGE_OFFSET BL33_BASE
Yann Gautier4b0c72a2018-07-16 10:54:09 +020085
86/*******************************************************************************
87 * DTB specific defines.
88 ******************************************************************************/
Yann Gautiera2e2a302019-02-14 11:13:39 +010089#define DTB_BASE STM32MP_DTB_BASE
90#define DTB_LIMIT (STM32MP_DTB_BASE + \
91 STM32MP_DTB_SIZE)
Yann Gautier4b0c72a2018-07-16 10:54:09 +020092
93/*******************************************************************************
94 * Platform specific page table and MMU setup constants
95 ******************************************************************************/
Yann Gautierf9d40d52019-01-17 14:41:46 +010096#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 32)
97#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 32)
Yann Gautier4b0c72a2018-07-16 10:54:09 +020098
99/*******************************************************************************
100 * Declarations and constants to access the mailboxes safely. Each mailbox is
101 * aligned on the biggest cache line size in the platform. This is known only
102 * to the platform as it might have a combination of integrated and external
103 * caches. Such alignment ensures that two maiboxes do not sit on the same cache
104 * line at any cache level. They could belong to different cpus/clusters &
105 * get written while being protected by different locks causing corruption of
106 * a valid mailbox address.
107 ******************************************************************************/
108#define CACHE_WRITEBACK_SHIFT 6
109#define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT)
110
111/*
112 * Secure Interrupt: based on the standard ARM mapping
113 */
114#define ARM_IRQ_SEC_PHY_TIMER U(29)
115
116#define ARM_IRQ_SEC_SGI_0 U(8)
117#define ARM_IRQ_SEC_SGI_1 U(9)
118#define ARM_IRQ_SEC_SGI_2 U(10)
119#define ARM_IRQ_SEC_SGI_3 U(11)
120#define ARM_IRQ_SEC_SGI_4 U(12)
121#define ARM_IRQ_SEC_SGI_5 U(13)
122#define ARM_IRQ_SEC_SGI_6 U(14)
123#define ARM_IRQ_SEC_SGI_7 U(15)
124
125#define STM32MP1_IRQ_TZC400 U(36)
126#define STM32MP1_IRQ_TAMPSERRS U(229)
127#define STM32MP1_IRQ_AXIERRIRQ U(244)
128
129/*
130 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
131 * terminology. On a GICv2 system or mode, the lists will be merged and treated
132 * as Group 0 interrupts.
133 */
134#define PLATFORM_G1S_PROPS(grp) \
135 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, \
136 GIC_HIGHEST_SEC_PRIORITY, \
137 grp, GIC_INTR_CFG_LEVEL), \
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200138 INTR_PROP_DESC(STM32MP1_IRQ_AXIERRIRQ, \
139 GIC_HIGHEST_SEC_PRIORITY, \
140 grp, GIC_INTR_CFG_LEVEL), \
141 INTR_PROP_DESC(STM32MP1_IRQ_TZC400, \
142 GIC_HIGHEST_SEC_PRIORITY, \
143 grp, GIC_INTR_CFG_LEVEL), \
144 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, \
145 GIC_HIGHEST_SEC_PRIORITY, \
146 grp, GIC_INTR_CFG_EDGE), \
147 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, \
148 GIC_HIGHEST_SEC_PRIORITY, \
149 grp, GIC_INTR_CFG_EDGE), \
150 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, \
151 GIC_HIGHEST_SEC_PRIORITY, \
152 grp, GIC_INTR_CFG_EDGE), \
153 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, \
154 GIC_HIGHEST_SEC_PRIORITY, \
155 grp, GIC_INTR_CFG_EDGE), \
156 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, \
157 GIC_HIGHEST_SEC_PRIORITY, \
158 grp, GIC_INTR_CFG_EDGE), \
159 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, \
160 GIC_HIGHEST_SEC_PRIORITY, \
161 grp, GIC_INTR_CFG_EDGE)
162
163#define PLATFORM_G0_PROPS(grp) \
164 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, \
165 GIC_HIGHEST_SEC_PRIORITY, \
166 grp, GIC_INTR_CFG_EDGE), \
167 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, \
168 GIC_HIGHEST_SEC_PRIORITY, \
169 grp, GIC_INTR_CFG_EDGE)
170
171/*
172 * Power
173 */
174#define PLAT_MAX_PWR_LVL U(1)
175
176/* Local power state for power domains in Run state. */
177#define ARM_LOCAL_STATE_RUN U(0)
178/* Local power state for retention. Valid only for CPU power domains */
179#define ARM_LOCAL_STATE_RET U(1)
180/* Local power state for power-down. Valid for CPU and cluster power domains */
181#define ARM_LOCAL_STATE_OFF U(2)
182/*
183 * This macro defines the deepest retention state possible.
184 * A higher state id will represent an invalid or a power down state.
185 */
186#define PLAT_MAX_RET_STATE ARM_LOCAL_STATE_RET
187/*
188 * This macro defines the deepest power down states possible. Any state ID
189 * higher than this is invalid.
190 */
191#define PLAT_MAX_OFF_STATE ARM_LOCAL_STATE_OFF
192
193/*******************************************************************************
194 * Size of the per-cpu data in bytes that should be reserved in the generic
195 * per-cpu data structure for the FVP port.
196 ******************************************************************************/
197#define PLAT_PCPU_DATA_SIZE 2
198
Etienne Carriere34f0e932020-07-16 17:36:18 +0200199/*******************************************************************************
200 * Number of parallel entry slots in SMT SCMI server entry context. For this
201 * platform, SCMI server is reached through SMC only, hence the number of
202 * entry slots.
203 ******************************************************************************/
204#define PLAT_SMT_ENTRY_COUNT PLATFORM_CORE_COUNT
205
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200206#endif /* PLATFORM_DEF_H */