| Yann Gautier | 4b0c72a | 2018-07-16 10:54:09 +0200 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef PLATFORM_DEF_H |
| 8 | #define PLATFORM_DEF_H |
| 9 | |
| 10 | #include <arch.h> |
| 11 | #include <common_def.h> |
| 12 | #include <gic_common.h> |
| 13 | #include <utils_def.h> |
| 14 | #include "../stm32mp1_def.h" |
| 15 | |
| 16 | /******************************************************************************* |
| 17 | * Generic platform constants |
| 18 | ******************************************************************************/ |
| 19 | |
| 20 | /* Size of cacheable stacks */ |
| 21 | #define PLATFORM_STACK_SIZE 0xC00 |
| 22 | |
| 23 | /* SSBL = second stage boot loader */ |
| 24 | #define BL33_IMAGE_NAME "ssbl" |
| 25 | |
| 26 | #define STM32MP1_PRIMARY_CPU U(0x0) |
| 27 | |
| 28 | #define PLATFORM_CACHE_LINE_SIZE 64 |
| 29 | #define PLATFORM_CLUSTER_COUNT ULL(1) |
| 30 | #define PLATFORM_CLUSTER0_CORE_COUNT U(2) |
| 31 | #define PLATFORM_CLUSTER1_CORE_COUNT U(0) |
| 32 | #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ |
| 33 | PLATFORM_CLUSTER0_CORE_COUNT) |
| 34 | #define PLATFORM_MAX_CPUS_PER_CLUSTER 2 |
| 35 | |
| 36 | #define MAX_IO_DEVICES 4 |
| 37 | #define MAX_IO_HANDLES 4 |
| 38 | |
| 39 | /******************************************************************************* |
| 40 | * BL2 specific defines. |
| 41 | ******************************************************************************/ |
| 42 | /* |
| 43 | * Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug |
| 44 | * size plus a little space for growth. |
| 45 | */ |
| 46 | #define BL2_BASE STM32MP1_BL2_BASE |
| 47 | #define BL2_LIMIT (STM32MP1_BL2_BASE + \ |
| 48 | STM32MP1_BL2_SIZE) |
| 49 | |
| 50 | /******************************************************************************* |
| 51 | * BL32 specific defines. |
| 52 | ******************************************************************************/ |
| 53 | #define BL32_BASE STM32MP1_BL32_BASE |
| 54 | #define BL32_LIMIT (STM32MP1_BL32_BASE + \ |
| 55 | STM32MP1_BL32_SIZE) |
| 56 | |
| 57 | /******************************************************************************* |
| 58 | * BL33 specific defines. |
| 59 | ******************************************************************************/ |
| 60 | #define BL33_BASE STM32MP1_BL33_BASE |
| 61 | |
| 62 | /* |
| 63 | * Load address of BL33 for this platform port |
| 64 | */ |
| 65 | #define PLAT_STM32MP1_NS_IMAGE_OFFSET BL33_BASE |
| 66 | |
| 67 | /******************************************************************************* |
| 68 | * DTB specific defines. |
| 69 | ******************************************************************************/ |
| 70 | #define DTB_BASE STM32MP1_DTB_BASE |
| 71 | #define DTB_LIMIT (STM32MP1_DTB_BASE + \ |
| 72 | STM32MP1_DTB_SIZE) |
| 73 | |
| 74 | /******************************************************************************* |
| 75 | * Platform specific page table and MMU setup constants |
| 76 | ******************************************************************************/ |
| 77 | #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) |
| 78 | #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) |
| 79 | |
| 80 | /******************************************************************************* |
| 81 | * Declarations and constants to access the mailboxes safely. Each mailbox is |
| 82 | * aligned on the biggest cache line size in the platform. This is known only |
| 83 | * to the platform as it might have a combination of integrated and external |
| 84 | * caches. Such alignment ensures that two maiboxes do not sit on the same cache |
| 85 | * line at any cache level. They could belong to different cpus/clusters & |
| 86 | * get written while being protected by different locks causing corruption of |
| 87 | * a valid mailbox address. |
| 88 | ******************************************************************************/ |
| 89 | #define CACHE_WRITEBACK_SHIFT 6 |
| 90 | #define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT) |
| 91 | |
| 92 | /* |
| 93 | * Secure Interrupt: based on the standard ARM mapping |
| 94 | */ |
| 95 | #define ARM_IRQ_SEC_PHY_TIMER U(29) |
| 96 | |
| 97 | #define ARM_IRQ_SEC_SGI_0 U(8) |
| 98 | #define ARM_IRQ_SEC_SGI_1 U(9) |
| 99 | #define ARM_IRQ_SEC_SGI_2 U(10) |
| 100 | #define ARM_IRQ_SEC_SGI_3 U(11) |
| 101 | #define ARM_IRQ_SEC_SGI_4 U(12) |
| 102 | #define ARM_IRQ_SEC_SGI_5 U(13) |
| 103 | #define ARM_IRQ_SEC_SGI_6 U(14) |
| 104 | #define ARM_IRQ_SEC_SGI_7 U(15) |
| 105 | |
| 106 | #define STM32MP1_IRQ_TZC400 U(36) |
| 107 | #define STM32MP1_IRQ_TAMPSERRS U(229) |
| 108 | #define STM32MP1_IRQ_AXIERRIRQ U(244) |
| 109 | |
| 110 | /* |
| 111 | * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 |
| 112 | * terminology. On a GICv2 system or mode, the lists will be merged and treated |
| 113 | * as Group 0 interrupts. |
| 114 | */ |
| 115 | #define PLATFORM_G1S_PROPS(grp) \ |
| 116 | INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, \ |
| 117 | GIC_HIGHEST_SEC_PRIORITY, \ |
| 118 | grp, GIC_INTR_CFG_LEVEL), \ |
| 119 | INTR_PROP_DESC(STM32MP1_IRQ_TAMPSERRS, \ |
| 120 | GIC_HIGHEST_SEC_PRIORITY, \ |
| 121 | grp, GIC_INTR_CFG_LEVEL), \ |
| 122 | INTR_PROP_DESC(STM32MP1_IRQ_AXIERRIRQ, \ |
| 123 | GIC_HIGHEST_SEC_PRIORITY, \ |
| 124 | grp, GIC_INTR_CFG_LEVEL), \ |
| 125 | INTR_PROP_DESC(STM32MP1_IRQ_TZC400, \ |
| 126 | GIC_HIGHEST_SEC_PRIORITY, \ |
| 127 | grp, GIC_INTR_CFG_LEVEL), \ |
| 128 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, \ |
| 129 | GIC_HIGHEST_SEC_PRIORITY, \ |
| 130 | grp, GIC_INTR_CFG_EDGE), \ |
| 131 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, \ |
| 132 | GIC_HIGHEST_SEC_PRIORITY, \ |
| 133 | grp, GIC_INTR_CFG_EDGE), \ |
| 134 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, \ |
| 135 | GIC_HIGHEST_SEC_PRIORITY, \ |
| 136 | grp, GIC_INTR_CFG_EDGE), \ |
| 137 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, \ |
| 138 | GIC_HIGHEST_SEC_PRIORITY, \ |
| 139 | grp, GIC_INTR_CFG_EDGE), \ |
| 140 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, \ |
| 141 | GIC_HIGHEST_SEC_PRIORITY, \ |
| 142 | grp, GIC_INTR_CFG_EDGE), \ |
| 143 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, \ |
| 144 | GIC_HIGHEST_SEC_PRIORITY, \ |
| 145 | grp, GIC_INTR_CFG_EDGE) |
| 146 | |
| 147 | #define PLATFORM_G0_PROPS(grp) \ |
| 148 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, \ |
| 149 | GIC_HIGHEST_SEC_PRIORITY, \ |
| 150 | grp, GIC_INTR_CFG_EDGE), \ |
| 151 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, \ |
| 152 | GIC_HIGHEST_SEC_PRIORITY, \ |
| 153 | grp, GIC_INTR_CFG_EDGE) |
| 154 | |
| 155 | /* |
| 156 | * Power |
| 157 | */ |
| 158 | #define PLAT_MAX_PWR_LVL U(1) |
| 159 | |
| 160 | /* Local power state for power domains in Run state. */ |
| 161 | #define ARM_LOCAL_STATE_RUN U(0) |
| 162 | /* Local power state for retention. Valid only for CPU power domains */ |
| 163 | #define ARM_LOCAL_STATE_RET U(1) |
| 164 | /* Local power state for power-down. Valid for CPU and cluster power domains */ |
| 165 | #define ARM_LOCAL_STATE_OFF U(2) |
| 166 | /* |
| 167 | * This macro defines the deepest retention state possible. |
| 168 | * A higher state id will represent an invalid or a power down state. |
| 169 | */ |
| 170 | #define PLAT_MAX_RET_STATE ARM_LOCAL_STATE_RET |
| 171 | /* |
| 172 | * This macro defines the deepest power down states possible. Any state ID |
| 173 | * higher than this is invalid. |
| 174 | */ |
| 175 | #define PLAT_MAX_OFF_STATE ARM_LOCAL_STATE_OFF |
| 176 | |
| 177 | /******************************************************************************* |
| 178 | * Size of the per-cpu data in bytes that should be reserved in the generic |
| 179 | * per-cpu data structure for the FVP port. |
| 180 | ******************************************************************************/ |
| 181 | #define PLAT_PCPU_DATA_SIZE 2 |
| 182 | |
| 183 | #endif /* PLATFORM_DEF_H */ |