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Dan Handley9df48042015-03-19 18:58:55 +00001/*
Javier Almansa Sobrino7176a772021-11-24 18:37:37 +00002 * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Dan Handley9df48042015-03-19 18:58:55 +00005 */
Antonio Nino Diaz05fdb832018-10-25 16:53:04 +01006#ifndef PLAT_ARM_H
7#define PLAT_ARM_H
Dan Handley9df48042015-03-19 18:58:55 +00008
Louis Mayencourt70d7c092020-01-29 11:42:31 +00009#include <stdbool.h>
Dan Handley9df48042015-03-19 18:58:55 +000010#include <stdint.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011
12#include <drivers/arm/tzc_common.h>
13#include <lib/bakery_lock.h>
14#include <lib/cassert.h>
15#include <lib/el3_runtime/cpu_data.h>
16#include <lib/spinlock.h>
17#include <lib/utils_def.h>
18#include <lib/xlat_tables/xlat_tables_compat.h>
Dan Handley9df48042015-03-19 18:58:55 +000019
Sandrine Bailleuxf402a522016-09-15 10:09:53 +010020/*******************************************************************************
21 * Forward declarations
22 ******************************************************************************/
Sandrine Bailleuxf402a522016-09-15 10:09:53 +010023struct meminfo;
Yatharth Kocharf9a0f162016-09-13 17:07:57 +010024struct image_info;
Soby Mathew96a1c6b2018-01-15 14:45:33 +000025struct bl_params;
Sandrine Bailleuxf402a522016-09-15 10:09:53 +010026
Summer Qin5ce394c2018-03-12 11:28:26 +080027typedef struct arm_tzc_regions_info {
28 unsigned long long base;
29 unsigned long long end;
Antonio Nino Diaz5f475792018-10-15 14:58:11 +010030 unsigned int sec_attr;
Summer Qin5ce394c2018-03-12 11:28:26 +080031 unsigned int nsaid_permissions;
32} arm_tzc_regions_info_t;
33
34/*******************************************************************************
35 * Default mapping definition of the TrustZone Controller for ARM standard
36 * platforms.
37 * Configure:
38 * - Region 0 with no access;
39 * - Region 1 with secure access only;
40 * - the remaining DRAM regions access from the given Non-Secure masters.
41 ******************************************************************************/
Paul Beesleyfe975b42019-09-16 11:29:03 +000042#if SPM_MM
Summer Qin5ce394c2018-03-12 11:28:26 +080043#define ARM_TZC_REGIONS_DEF \
Zelalem Awekec43c5632021-07-12 23:41:05 -050044 {ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END + ARM_L1_GPT_SIZE,\
Summer Qin5ce394c2018-03-12 11:28:26 +080045 TZC_REGION_S_RDWR, 0}, \
46 {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \
47 PLAT_ARM_TZC_NS_DEV_ACCESS}, \
48 {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \
49 PLAT_ARM_TZC_NS_DEV_ACCESS}, \
Ard Biesheuvel8b034fc2018-12-29 19:43:21 +010050 {PLAT_SP_IMAGE_NS_BUF_BASE, (PLAT_SP_IMAGE_NS_BUF_BASE + \
51 PLAT_SP_IMAGE_NS_BUF_SIZE) - 1, TZC_REGION_S_NONE, \
Summer Qin5ce394c2018-03-12 11:28:26 +080052 PLAT_ARM_TZC_NS_DEV_ACCESS}
53
Zelalem Awekec43c5632021-07-12 23:41:05 -050054#elif ENABLE_RME
55#define ARM_TZC_REGIONS_DEF \
56 {ARM_AP_TZC_DRAM1_BASE, ARM_AP_TZC_DRAM1_END, TZC_REGION_S_RDWR, 0},\
57 {ARM_EL3_TZC_DRAM1_BASE, ARM_L1_GPT_END, TZC_REGION_S_RDWR, 0}, \
58 {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \
59 PLAT_ARM_TZC_NS_DEV_ACCESS}, \
Javier Almansa Sobrino7176a772021-11-24 18:37:37 +000060 /* Realm and Shared area share the same PAS */ \
61 {ARM_REALM_BASE, ARM_EL3_RMM_SHARED_END, ARM_TZC_NS_DRAM_S_ACCESS, \
Zelalem Awekec43c5632021-07-12 23:41:05 -050062 PLAT_ARM_TZC_NS_DEV_ACCESS}, \
63 {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \
64 PLAT_ARM_TZC_NS_DEV_ACCESS}
65
Summer Qin5ce394c2018-03-12 11:28:26 +080066#else
67#define ARM_TZC_REGIONS_DEF \
Zelalem Awekec43c5632021-07-12 23:41:05 -050068 {ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END + ARM_L1_GPT_SIZE,\
Summer Qin5ce394c2018-03-12 11:28:26 +080069 TZC_REGION_S_RDWR, 0}, \
70 {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \
71 PLAT_ARM_TZC_NS_DEV_ACCESS}, \
72 {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \
73 PLAT_ARM_TZC_NS_DEV_ACCESS}
74#endif
75
Chris Kay2b54c0c2018-05-09 15:46:07 +010076#define ARM_CASSERT_MMAP \
77 CASSERT((ARRAY_SIZE(plat_arm_mmap) - 1) <= PLAT_ARM_MMAP_ENTRIES, \
78 assert_plat_arm_mmap_mismatch); \
79 CASSERT((PLAT_ARM_MMAP_ENTRIES + ARM_BL_REGIONS) \
80 <= MAX_MMAP_REGIONS, \
Dan Handley9df48042015-03-19 18:58:55 +000081 assert_max_mmap_regions);
82
Roberto Vargase3adc372018-05-23 09:27:06 +010083void arm_setup_romlib(void);
84
Julius Werner8e0ef0f2019-07-09 14:02:43 -070085#if defined(IMAGE_BL31) || (!defined(__aarch64__) && defined(IMAGE_BL32))
Dan Handley9df48042015-03-19 18:58:55 +000086/*
87 * Use this macro to instantiate lock before it is used in below
88 * arm_lock_xxx() macros
89 */
Sandrine Bailleuxceb258e2018-07-11 13:59:18 +020090#define ARM_INSTANTIATE_LOCK static DEFINE_BAKERY_LOCK(arm_lock)
Soby Mathewea26bad2016-11-14 12:25:45 +000091#define ARM_LOCK_GET_INSTANCE (&arm_lock)
Roberto Vargas00996942017-11-13 13:41:58 +000092
93#if !HW_ASSISTED_COHERENCY
94#define ARM_SCMI_INSTANTIATE_LOCK DEFINE_BAKERY_LOCK(arm_scmi_lock)
95#else
96#define ARM_SCMI_INSTANTIATE_LOCK spinlock_t arm_scmi_lock
97#endif
98#define ARM_SCMI_LOCK_GET_INSTANCE (&arm_scmi_lock)
99
Dan Handley9df48042015-03-19 18:58:55 +0000100/*
101 * These are wrapper macros to the Coherent Memory Bakery Lock API.
102 */
103#define arm_lock_init() bakery_lock_init(&arm_lock)
104#define arm_lock_get() bakery_lock_get(&arm_lock)
105#define arm_lock_release() bakery_lock_release(&arm_lock)
106
107#else
108
Dan Handley9df48042015-03-19 18:58:55 +0000109/*
Yatharth Kochar2694cba2016-11-14 12:00:41 +0000110 * Empty macros for all other BL stages other than BL31 and BL32
Dan Handley9df48042015-03-19 18:58:55 +0000111 */
Jeenu Viswambharan749d25b2017-08-23 14:12:59 +0100112#define ARM_INSTANTIATE_LOCK static int arm_lock __unused
Soby Mathewea26bad2016-11-14 12:25:45 +0000113#define ARM_LOCK_GET_INSTANCE 0
Dan Handley9df48042015-03-19 18:58:55 +0000114#define arm_lock_init()
115#define arm_lock_get()
116#define arm_lock_release()
117
Julius Werner8e0ef0f2019-07-09 14:02:43 -0700118#endif /* defined(IMAGE_BL31) || (!defined(__aarch64__) && defined(IMAGE_BL32)) */
Dan Handley9df48042015-03-19 18:58:55 +0000119
Soby Mathew7799cf72015-04-16 14:49:09 +0100120#if ARM_RECOM_STATE_ID_ENC
121/*
122 * Macros used to parse state information from State-ID if it is using the
123 * recommended encoding for State-ID.
124 */
125#define ARM_LOCAL_PSTATE_WIDTH 4
126#define ARM_LOCAL_PSTATE_MASK ((1 << ARM_LOCAL_PSTATE_WIDTH) - 1)
127
128/* Macros to construct the composite power state */
129
130/* Make composite power state parameter till power level 0 */
131#if PSCI_EXTENDED_STATE_ID
132
133#define arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \
134 (((lvl0_state) << PSTATE_ID_SHIFT) | ((type) << PSTATE_TYPE_SHIFT))
135#else
136#define arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \
137 (((lvl0_state) << PSTATE_ID_SHIFT) | \
138 ((pwr_lvl) << PSTATE_PWR_LVL_SHIFT) | \
139 ((type) << PSTATE_TYPE_SHIFT))
140#endif /* __PSCI_EXTENDED_STATE_ID__ */
141
142/* Make composite power state parameter till power level 1 */
143#define arm_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type) \
144 (((lvl1_state) << ARM_LOCAL_PSTATE_WIDTH) | \
145 arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type))
146
Soby Mathewa869de12015-05-08 10:18:59 +0100147/* Make composite power state parameter till power level 2 */
148#define arm_make_pwrstate_lvl2(lvl2_state, lvl1_state, lvl0_state, pwr_lvl, type) \
149 (((lvl2_state) << (ARM_LOCAL_PSTATE_WIDTH * 2)) | \
150 arm_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type))
151
Soby Mathew7799cf72015-04-16 14:49:09 +0100152#endif /* __ARM_RECOM_STATE_ID_ENC__ */
153
Jeenu Viswambharanbc1a9292017-02-16 14:55:15 +0000154/* ARM State switch error codes */
155#define STATE_SW_E_PARAM (-2)
156#define STATE_SW_E_DENIED (-3)
Dan Handley9df48042015-03-19 18:58:55 +0000157
Max Shvetsov06dba292019-12-06 11:50:12 +0000158/* plat_get_rotpk_info() flags */
159#define ARM_ROTPK_REGS_ID 1
160#define ARM_ROTPK_DEVEL_RSA_ID 2
161#define ARM_ROTPK_DEVEL_ECDSA_ID 3
laurenw-arm055199b2022-10-28 11:26:32 -0500162#define ARM_ROTPK_DEVEL_FULL_DEV_RSA_KEY_ID 4
Manish V Badarkhef809c6e2020-02-22 08:43:00 +0000163
Dan Handley9df48042015-03-19 18:58:55 +0000164/* IO storage utility functions */
Louis Mayencourt7d24ce12020-01-29 14:43:06 +0000165int arm_io_setup(void);
Dan Handley9df48042015-03-19 18:58:55 +0000166
Manish V Badarkhedd6f2522021-02-22 17:30:17 +0000167/* Set image specification in IO block policy */
Manish V Badarkhed2f0a7a2021-06-25 23:43:33 +0100168int arm_set_image_source(unsigned int image_id, const char *part_name,
169 uintptr_t *dev_handle, uintptr_t *image_spec);
170void arm_set_fip_addr(uint32_t active_fw_bank_idx);
Manish V Badarkhedd6f2522021-02-22 17:30:17 +0000171
Dan Handley9df48042015-03-19 18:58:55 +0000172/* Security utility functions */
Suyash Pathakb71a9e62020-02-04 13:55:20 +0530173void arm_tzc400_setup(uintptr_t tzc_base,
174 const arm_tzc_regions_info_t *tzc_regions);
Vikram Kanigiri510d87b2016-01-29 12:32:58 +0000175struct tzc_dmc500_driver_data;
Summer Qin5ce394c2018-03-12 11:28:26 +0800176void arm_tzc_dmc500_setup(struct tzc_dmc500_driver_data *plat_driver_data,
177 const arm_tzc_regions_info_t *tzc_regions);
Dan Handley9df48042015-03-19 18:58:55 +0000178
Antonio Nino Diaz23ede6a2018-06-19 09:29:36 +0100179/* Console utility functions */
180void arm_console_boot_init(void);
181void arm_console_boot_end(void);
182void arm_console_runtime_init(void);
183void arm_console_runtime_end(void);
184
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100185/* Systimer utility function */
186void arm_configure_sys_timer(void);
187
Dan Handley9df48042015-03-19 18:58:55 +0000188/* PM utility functions */
Soby Mathewfec4eb72015-07-01 16:16:20 +0100189int arm_validate_power_state(unsigned int power_state,
190 psci_power_state_t *req_state);
Jeenu Viswambharan59424d82017-09-19 09:27:18 +0100191int arm_validate_psci_entrypoint(uintptr_t entrypoint);
Soby Mathew0d9e8522015-07-15 13:36:24 +0100192int arm_validate_ns_entrypoint(uintptr_t entrypoint);
Soby Mathew9ca28062017-10-11 16:08:58 +0100193void arm_system_pwr_domain_save(void);
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100194void arm_system_pwr_domain_resume(void);
Roberto Vargas1a6eed32018-02-12 12:36:17 +0000195int arm_psci_read_mem_protect(int *enabled);
Roberto Vargasa1c16b62017-08-03 09:16:43 +0100196int arm_nor_psci_write_mem_protect(int val);
Roberto Vargas550eb082018-01-05 16:00:05 +0000197void arm_nor_psci_do_static_mem_protect(void);
198void arm_nor_psci_do_dyn_mem_protect(void);
Roberto Vargasa1c16b62017-08-03 09:16:43 +0100199int arm_psci_mem_protect_chk(uintptr_t base, u_register_t length);
Soby Mathewfec4eb72015-07-01 16:16:20 +0100200
201/* Topology utility function */
202int arm_check_mpidr(u_register_t mpidr);
Dan Handley9df48042015-03-19 18:58:55 +0000203
204/* BL1 utility functions */
205void arm_bl1_early_platform_setup(void);
206void arm_bl1_platform_setup(void);
207void arm_bl1_plat_arch_setup(void);
208
209/* BL2 utility functions */
Manish V Badarkhe99a8e142020-06-11 22:32:11 +0100210void arm_bl2_early_platform_setup(uintptr_t fw_config, struct meminfo *mem_layout);
Dan Handley9df48042015-03-19 18:58:55 +0000211void arm_bl2_platform_setup(void);
212void arm_bl2_plat_arch_setup(void);
213uint32_t arm_get_spsr_for_bl32_entry(void);
214uint32_t arm_get_spsr_for_bl33_entry(void);
Ambroise Vincentb237bca2019-02-13 15:58:00 +0000215int arm_bl2_plat_handle_post_image_load(unsigned int image_id);
Yatharth Kocharede39cb2016-11-14 12:01:04 +0000216int arm_bl2_handle_post_image_load(unsigned int image_id);
Sathees Balya90950092018-11-15 14:22:30 +0000217struct bl_params *arm_get_next_bl_params(void);
Dan Handley9df48042015-03-19 18:58:55 +0000218
Roberto Vargas52207802017-11-17 13:22:18 +0000219/* BL2 at EL3 functions */
220void arm_bl2_el3_early_platform_setup(void);
221void arm_bl2_el3_plat_arch_setup(void);
222
Yatharth Kochar3a11eda2015-10-14 15:28:11 +0100223/* BL2U utility functions */
224void arm_bl2u_early_platform_setup(struct meminfo *mem_layout,
225 void *plat_info);
226void arm_bl2u_platform_setup(void);
227void arm_bl2u_plat_arch_setup(void);
228
Juan Castillo7d199412015-12-14 09:35:25 +0000229/* BL31 utility functions */
Soby Mathew7d5a2e72018-01-10 15:59:31 +0000230void arm_bl31_early_platform_setup(void *from_bl2, uintptr_t soc_fw_config,
231 uintptr_t hw_config, void *plat_params_from_bl2);
Dan Handley9df48042015-03-19 18:58:55 +0000232void arm_bl31_platform_setup(void);
Soby Mathew2fd66be2015-12-09 11:38:43 +0000233void arm_bl31_plat_runtime_setup(void);
Dan Handley9df48042015-03-19 18:58:55 +0000234void arm_bl31_plat_arch_setup(void);
235
236/* TSP utility functions */
237void arm_tsp_early_platform_setup(void);
238
Soby Mathew7b754182016-07-11 14:15:27 +0100239/* SP_MIN utility functions */
Soby Mathew7d5a2e72018-01-10 15:59:31 +0000240void arm_sp_min_early_platform_setup(void *from_bl2, uintptr_t tos_fw_config,
241 uintptr_t hw_config, void *plat_params_from_bl2);
Dimitris Papastamos52323b02017-06-07 13:45:41 +0100242void arm_sp_min_plat_runtime_setup(void);
Madhukar Pappireddyae9677b2020-01-27 13:37:51 -0600243void arm_sp_min_plat_arch_setup(void);
Soby Mathew7b754182016-07-11 14:15:27 +0100244
Yatharth Kochar736a3bf2015-10-11 14:14:55 +0100245/* FIP TOC validity check */
Louis Mayencourt70d7c092020-01-29 11:42:31 +0000246bool arm_io_is_toc_valid(void);
Dan Handley9df48042015-03-19 18:58:55 +0000247
Soby Mathew7c6df5b2018-01-15 14:43:42 +0000248/* Utility functions for Dynamic Config */
Soby Mathew96a1c6b2018-01-15 14:45:33 +0000249void arm_bl2_dyn_cfg_init(void);
John Tsichritzisc34341a2018-07-30 13:41:52 +0100250void arm_bl1_set_mbedtls_heap(void);
251int arm_get_mbedtls_heap(void **heap_addr, size_t *heap_size);
Soby Mathew7c6df5b2018-01-15 14:43:42 +0000252
Alexei Fedorov25d7c882020-03-20 18:38:55 +0000253#if MEASURED_BOOT
Manish V Badarkhe7ca9d652021-09-14 22:41:46 +0100254int arm_set_tos_fw_info(uintptr_t log_addr, size_t log_size);
255int arm_set_nt_fw_info(
Alexei Fedorovc7176172020-07-13 12:11:05 +0100256/*
257 * Currently OP-TEE does not support reading DTBs from Secure memory
258 * and this option should be removed when feature is supported.
259 */
260#ifdef SPD_opteed
261 uintptr_t log_addr,
Alexei Fedorov25d7c882020-03-20 18:38:55 +0000262#endif
Alexei Fedorovc7176172020-07-13 12:11:05 +0100263 size_t log_size, uintptr_t *ns_log_addr);
Manish V Badarkhe4edf4bd2021-08-11 10:45:03 +0100264int arm_set_tb_fw_info(uintptr_t log_addr, size_t log_size);
265int arm_get_tb_fw_info(uint64_t *log_addr, size_t *log_size);
Alexei Fedorovc7176172020-07-13 12:11:05 +0100266#endif /* MEASURED_BOOT */
Alexei Fedorov25d7c882020-03-20 18:38:55 +0000267
Dan Handley9df48042015-03-19 18:58:55 +0000268/*
Daniel Boulbyb1b058d2018-09-18 11:52:49 +0100269 * Free the memory storing initialization code only used during an images boot
270 * time so it can be reclaimed for runtime data
271 */
272void arm_free_init_memory(void);
273
274/*
Petre-Ionut Tudore5a6fef2019-11-07 15:18:03 +0000275 * Make the higher level translation tables read-only
276 */
277void arm_xlat_make_tables_readonly(void);
278
279/*
Dan Handley9df48042015-03-19 18:58:55 +0000280 * Mandatory functions required in ARM standard platforms
281 */
Soby Mathew47e43f22016-02-01 14:04:34 +0000282unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr);
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000283void plat_arm_gic_driver_init(void);
Dan Handley9df48042015-03-19 18:58:55 +0000284void plat_arm_gic_init(void);
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000285void plat_arm_gic_cpuif_enable(void);
286void plat_arm_gic_cpuif_disable(void);
Jeenu Viswambharan78132c92016-12-09 11:12:34 +0000287void plat_arm_gic_redistif_on(void);
288void plat_arm_gic_redistif_off(void);
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000289void plat_arm_gic_pcpu_init(void);
Soby Mathew9ca28062017-10-11 16:08:58 +0100290void plat_arm_gic_save(void);
291void plat_arm_gic_resume(void);
Dan Handley9df48042015-03-19 18:58:55 +0000292void plat_arm_security_setup(void);
293void plat_arm_pwrc_setup(void);
Vikram Kanigirifbb13012016-02-15 11:54:14 +0000294void plat_arm_interconnect_init(void);
295void plat_arm_interconnect_enter_coherency(void);
296void plat_arm_interconnect_exit_coherency(void);
Dimitris Papastamosd7a36512018-06-18 13:01:06 +0100297void plat_arm_program_trusted_mailbox(uintptr_t address);
Louis Mayencourt70d7c092020-01-29 11:42:31 +0000298bool plat_arm_bl1_fwu_needed(void);
Ambroise Vincentfa42c9e2019-07-04 14:58:45 +0100299__dead2 void plat_arm_error_handler(int err);
Manish V Badarkhefcfe4312022-07-12 21:48:04 +0100300__dead2 void plat_arm_system_reset(void);
Dan Handley9df48042015-03-19 18:58:55 +0000301
Vijayenthiran Subramaniam2dfa7642019-10-11 14:01:25 +0530302/*
Max Shvetsov06dba292019-12-06 11:50:12 +0000303 * Optional functions in ARM standard platforms
Vijayenthiran Subramaniam2dfa7642019-10-11 14:01:25 +0530304 */
305void plat_arm_override_gicr_frames(const uintptr_t *plat_gicr_frames);
Sandrine Bailleux7b7a41c2020-02-06 14:34:44 +0100306int arm_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len,
Max Shvetsov06dba292019-12-06 11:50:12 +0000307 unsigned int *flags);
308int arm_get_rotpk_info_regs(void **key_ptr, unsigned int *key_len,
309 unsigned int *flags);
310int arm_get_rotpk_info_cc(void **key_ptr, unsigned int *key_len,
311 unsigned int *flags);
312int arm_get_rotpk_info_dev(void **key_ptr, unsigned int *key_len,
313 unsigned int *flags);
Vijayenthiran Subramaniam2dfa7642019-10-11 14:01:25 +0530314
Summer Qin93c812f2017-02-28 16:46:17 +0000315#if ARM_PLAT_MT
316unsigned int plat_arm_get_cpu_pe_count(u_register_t mpidr);
317#endif
318
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100319/*
320 * This function is called after loading SCP_BL2 image and it is used to perform
321 * any platform-specific actions required to handle the SCP firmware.
322 */
323int plat_arm_bl2_handle_scp_bl2(struct image_info *scp_bl2_image_info);
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100324
Dan Handley9df48042015-03-19 18:58:55 +0000325/*
326 * Optional functions required in ARM standard platforms
327 */
328void plat_arm_io_setup(void);
329int plat_arm_get_alt_image_source(
Juan Castillo3a66aca2015-04-13 17:36:19 +0100330 unsigned int image_id,
331 uintptr_t *dev_handle,
332 uintptr_t *image_spec);
Soby Mathewfec4eb72015-07-01 16:16:20 +0100333unsigned int plat_arm_calc_core_pos(u_register_t mpidr);
Vikram Kanigiri07035432015-11-12 18:52:34 +0000334const mmap_region_t *plat_arm_get_mmap(void);
Dan Handley9df48042015-03-19 18:58:55 +0000335
Soby Mathew0b4c5a32016-10-21 17:51:22 +0100336/* Allow platform to override psci_pm_ops during runtime */
337const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops);
338
Jeenu Viswambharanbc1a9292017-02-16 14:55:15 +0000339/* Execution state switch in ARM platforms */
340int arm_execution_state_switch(unsigned int smc_fid,
341 uint32_t pc_hi,
342 uint32_t pc_lo,
343 uint32_t cookie_hi,
344 uint32_t cookie_lo,
345 void *handle);
346
Soby Mathew6d07e672018-03-01 10:53:33 +0000347/* Optional functions for SP_MIN */
348void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1,
349 u_register_t arg2, u_register_t arg3);
350
Roberto Vargas2ca18d92018-02-12 12:36:17 +0000351/* global variables */
352extern plat_psci_ops_t plat_arm_psci_pm_ops;
353extern const mmap_region_t plat_arm_mmap[];
Jeenu Viswambharan4542cfe2018-07-19 08:03:46 +0100354extern const unsigned int arm_pm_idle_states[];
Roberto Vargas2ca18d92018-02-12 12:36:17 +0000355
Aditya Angadi20b48412019-04-16 11:29:14 +0530356/* secure watchdog */
357void plat_arm_secure_wdt_start(void);
358void plat_arm_secure_wdt_stop(void);
359
Manish V Badarkhef809c6e2020-02-22 08:43:00 +0000360/* Get SOC-ID of ARM platform */
361uint32_t plat_arm_get_soc_id(void);
362
Antonio Nino Diaz05fdb832018-10-25 16:53:04 +0100363#endif /* PLAT_ARM_H */