Gitiles
Code Review Sign In
git01.mediatek.com / filogic / atf / aac0c3c1c0105b6348ce61e825103fcd210b3fe0 / . / plat / arm / board / neoverse_rd / common / nrd-common.mk
blob: 96e6f01f877000448b9b4e12165a2331a742dd17 [file] [log] [blame]
Nariman Poushin0ece80f2018-02-26 06:52:04 +0000[diff] [blame]1#
Pranav Madhue7fa8fb2024-01-22 21:41:14 +0530[diff] [blame]2# Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
Nariman Poushin0ece80f2018-02-26 06:52:04 +0000[diff] [blame]3#
4# SPDX-License-Identifier: BSD-3-Clause
5#
6
Chandni Cherukurid61a7052018-08-01 15:58:48 +0530[diff] [blame]7CSS_USE_SCMI_SDS_DRIVER := 1
8
Rohit Mathew20d4a212024-02-03 21:20:17 +0000[diff] [blame]9NRD_COMMON_BASE := plat/arm/board/neoverse_rd/common
Nariman Poushin0ece80f2018-02-26 06:52:04 +0000[diff] [blame]10
Manish Pandeyd419e222023-02-13 12:39:17 +0000[diff] [blame]11ENABLE_FEAT_RAS := 1
12
Sughosh Ganu3f7e79d2018-05-16 18:48:56 +0530[diff] [blame]13SDEI_SUPPORT := 0
14
15EL3_EXCEPTION_HANDLING := 0
16
Manish Pandey0e3379d2022-10-10 11:43:08 +0100[diff] [blame]17HANDLE_EA_EL3_FIRST_NS := 0
Sughosh Ganu3f7e79d2018-05-16 18:48:56 +0530[diff] [blame]18
Rohit Mathew644d9e22024-02-03 19:06:16 +0000[diff] [blame]19NRD_CHIP_COUNT := 1
Vijayenthiran Subramaniambc489912019-12-26 17:45:58 +0530[diff] [blame]20
Rohit Mathew644d9e22024-02-03 19:06:16 +0000[diff] [blame]21NRD_PLATFORM_VARIANT := 0
Aditya Angadi06402222021-03-20 12:06:15 +0530[diff] [blame]22
Vijayenthiran Subramaniam063bb732021-11-25 21:54:30 +0530[diff] [blame]23# Do not enable SVE
24ENABLE_SVE_FOR_NS := 0
25
Nishant Sharma469a6f62022-04-19 10:23:59 +0100[diff] [blame]26CTX_INCLUDE_FPREGS := 1
27
Rohit Mathew20d4a212024-02-03 21:20:17 +0000[diff] [blame]28INTERCONNECT_SOURCES := ${NRD_COMMON_BASE}/nrd_interconnect.c
Nariman Poushin0ece80f2018-02-26 06:52:04 +0000[diff] [blame]29
Rohit Mathew20d4a212024-02-03 21:20:17 +0000[diff] [blame]30PLAT_INCLUDES += -I${NRD_COMMON_BASE}/include
Nariman Poushin0ece80f2018-02-26 06:52:04 +0000[diff] [blame]31
Alexei Fedorov84f1b5d2020-03-23 18:45:17 +0000[diff] [blame]32# GIC-600 configuration
Andre Przywarae1cc1302020-03-25 15:50:38 +0000[diff] [blame]33GICV3_SUPPORT_GIC600 := 1
Alexei Fedorov84f1b5d2020-03-23 18:45:17 +0000[diff] [blame]34
35# Include GICv3 driver files
36include drivers/arm/gic/v3/gicv3.mk
Nariman Poushin0ece80f2018-02-26 06:52:04 +0000[diff] [blame]37
Alexei Fedorov84f1b5d2020-03-23 18:45:17 +0000[diff] [blame]38ENT_GIC_SOURCES := ${GICV3_SOURCES} \
39 plat/common/plat_gicv3.c \
40 plat/arm/common/arm_gicv3.c
Nariman Poushin0ece80f2018-02-26 06:52:04 +0000[diff] [blame]41
Rohit Mathew20d4a212024-02-03 21:20:17 +0000[diff] [blame]42PLAT_BL_COMMON_SOURCES += ${NRD_COMMON_BASE}/arch/aarch64/nrd_helper.S
Nariman Poushin0ece80f2018-02-26 06:52:04 +0000[diff] [blame]43
Aditya Angadi20b48412019-04-16 11:29:14 +0530[diff] [blame]44BL1_SOURCES += ${INTERCONNECT_SOURCES} \
45 drivers/arm/sbsa/sbsa.c
Nariman Poushin0ece80f2018-02-26 06:52:04 +0000[diff] [blame]46
Rohit Mathew20d4a212024-02-03 21:20:17 +0000[diff] [blame]47BL2_SOURCES += ${NRD_COMMON_BASE}/nrd_image_load.c \
Nishant Sharma289f7822021-11-30 09:31:48 +0000[diff] [blame]48 drivers/arm/css/sds/sds.c
Nariman Poushin0ece80f2018-02-26 06:52:04 +0000[diff] [blame]49
Chandni Cherukuria3f66132018-08-10 11:17:58 +0530[diff] [blame]50BL31_SOURCES += ${INTERCONNECT_SOURCES} \
Nariman Poushin0ece80f2018-02-26 06:52:04 +0000[diff] [blame]51 ${ENT_GIC_SOURCES} \
Rohit Mathew20d4a212024-02-03 21:20:17 +0000[diff] [blame]52 ${NRD_COMMON_BASE}/nrd_bl31_setup.c \
53 ${NRD_COMMON_BASE}/nrd_topology.c \
Pranav Madhue7fa8fb2024-01-22 21:41:14 +0530[diff] [blame]54 drivers/delay_timer/generic_delay_timer.c
Nariman Poushin0ece80f2018-02-26 06:52:04 +0000[diff] [blame]55
Deepak Pandeyb0971f92018-05-25 12:43:30 +0530[diff] [blame]56ifneq (${RESET_TO_BL31},0)
Sandrine Bailleux1e32d322019-01-07 15:35:37 +0100[diff] [blame]57 $(error "Using BL31 as the reset vector is not supported on ${PLAT} platform. \
Deepak Pandeyb0971f92018-05-25 12:43:30 +0530[diff] [blame]58 Please set RESET_TO_BL31 to 0.")
59endif
60
Rohit Mathew644d9e22024-02-03 19:06:16 +0000[diff] [blame]61$(eval $(call add_define,NRD_CHIP_COUNT))
Vijayenthiran Subramaniambc489912019-12-26 17:45:58 +0530[diff] [blame]62
Rohit Mathew644d9e22024-02-03 19:06:16 +0000[diff] [blame]63$(eval $(call add_define,NRD_PLATFORM_VARIANT))
Aditya Angadi06402222021-03-20 12:06:15 +0530[diff] [blame]64
Nariman Poushin0ece80f2018-02-26 06:52:04 +0000[diff] [blame]65override CSS_LOAD_SCP_IMAGES := 0
66override NEED_BL2U := no
Sudipto Paulc4510102018-04-16 17:46:50 +0530[diff] [blame]67override ARM_PLAT_MT := 1
Pranav Madhu4c474322021-04-20 12:01:46 +0530[diff] [blame]68override PSCI_EXTENDED_STATE_ID := 1
69override ARM_RECOM_STATE_ID_ENC := 1
Nariman Poushin0ece80f2018-02-26 06:52:04 +0000[diff] [blame]70
71# System coherency is managed in hardware
72HW_ASSISTED_COHERENCY := 1
73
74# When building for systems with hardware-assisted coherency, there's no need to
75# use USE_COHERENT_MEM. Require that USE_COHERENT_MEM must be set to 0 too.
76USE_COHERENT_MEM := 0
77
78include plat/arm/common/arm_common.mk
79include plat/arm/css/common/css_common.mk
80include plat/arm/soc/common/soc_css.mk
81include plat/arm/board/common/board_common.mk