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Varun Wadekarb316e242015-05-19 16:48:04 +05301/*
Anthony Zhou59fd6152017-03-13 15:34:08 +08002 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
Varun Wadekarb316e242015-05-19 16:48:04 +05303 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Varun Wadekarb316e242015-05-19 16:48:04 +05305 */
6
7#ifndef __TEGRA_PRIVATE_H__
8#define __TEGRA_PRIVATE_H__
9
Varun Wadekara78bb1b2015-08-07 10:03:00 +053010#include <arch.h>
Varun Wadekarb316e242015-05-19 16:48:04 +053011#include <platform_def.h>
Yatharth Kochar33f5c412015-12-09 14:22:47 +000012#include <psci.h>
Varun Wadekara78bb1b2015-08-07 10:03:00 +053013#include <xlat_tables.h>
Varun Wadekarb316e242015-05-19 16:48:04 +053014
Varun Wadekar7a269e22015-06-10 14:04:32 +053015/*******************************************************************************
16 * Tegra DRAM memory base address
17 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -070018#define TEGRA_DRAM_BASE ULL(0x80000000)
19#define TEGRA_DRAM_END ULL(0x27FFFFFFF)
Varun Wadekar7a269e22015-06-10 14:04:32 +053020
Varun Wadekarb7b45752015-12-28 14:55:41 -080021/*******************************************************************************
22 * Struct for parameters received from BL2
23 ******************************************************************************/
Varun Wadekarb316e242015-05-19 16:48:04 +053024typedef struct plat_params_from_bl2 {
Varun Wadekar6bb62462015-10-06 12:49:31 +053025 /* TZ memory size */
Varun Wadekarb316e242015-05-19 16:48:04 +053026 uint64_t tzdram_size;
Varun Wadekar6bb62462015-10-06 12:49:31 +053027 /* TZ memory base */
28 uint64_t tzdram_base;
Varun Wadekard2014c62015-10-29 10:37:28 +053029 /* UART port ID */
30 int uart_id;
Varun Wadekarb316e242015-05-19 16:48:04 +053031} plat_params_from_bl2_t;
32
Varun Wadekardc799302015-12-28 16:36:42 -080033/*******************************************************************************
34 * Per-CPU struct describing FIQ state to be stored
35 ******************************************************************************/
36typedef struct pcpu_fiq_state {
37 uint64_t elr_el3;
38 uint64_t spsr_el3;
39} pcpu_fiq_state_t;
40
Varun Wadekarc6c386d2016-05-20 16:21:22 -070041/*******************************************************************************
42 * Struct describing per-FIQ configuration settings
43 ******************************************************************************/
44typedef struct irq_sec_cfg {
45 /* IRQ number */
46 unsigned int irq;
47 /* Target CPUs servicing this interrupt */
48 unsigned int target_cpus;
49 /* type = INTR_TYPE_S_EL1 or INTR_TYPE_EL3 */
50 uint32_t type;
51} irq_sec_cfg_t;
52
Varun Wadekar254441d2015-07-23 10:07:54 +053053/* Declarations for plat_psci_handlers.c */
Varun Wadekara78bb1b2015-08-07 10:03:00 +053054int32_t tegra_soc_validate_power_state(unsigned int power_state,
55 psci_power_state_t *req_state);
Varun Wadekar254441d2015-07-23 10:07:54 +053056
Varun Wadekarb316e242015-05-19 16:48:04 +053057/* Declarations for plat_setup.c */
58const mmap_region_t *plat_get_mmio_map(void);
Varun Wadekard2014c62015-10-29 10:37:28 +053059uint32_t plat_get_console_from_id(int id);
Varun Wadekarb7b45752015-12-28 14:55:41 -080060void plat_gic_setup(void);
Varun Wadekard22d4ad2016-05-23 11:41:07 -070061bl31_params_t *plat_get_bl31_params(void);
62plat_params_from_bl2_t *plat_get_bl31_plat_params(void);
Varun Wadekarb316e242015-05-19 16:48:04 +053063
64/* Declarations for plat_secondary.c */
65void plat_secondary_setup(void);
66int plat_lock_cpu_vectors(void);
67
Varun Wadekardc799302015-12-28 16:36:42 -080068/* Declarations for tegra_fiq_glue.c */
69void tegra_fiq_handler_setup(void);
70int tegra_fiq_get_intr_context(void);
71void tegra_fiq_set_ns_entrypoint(uint64_t entrypoint);
72
Varun Wadekarb316e242015-05-19 16:48:04 +053073/* Declarations for tegra_gic.c */
Varun Wadekarb316e242015-05-19 16:48:04 +053074void tegra_gic_cpuif_deactivate(void);
Varun Wadekarca872932017-05-25 18:06:59 -070075void tegra_gic_setup(const irq_sec_cfg_t *irq_sec_ptr, uint32_t num_irqs);
Varun Wadekarb316e242015-05-19 16:48:04 +053076
77/* Declarations for tegra_security.c */
78void tegra_security_setup(void);
79void tegra_security_setup_videomem(uintptr_t base, uint64_t size);
80
81/* Declarations for tegra_pm.c */
Vignesh Radhakrishnanb4a72942017-03-03 10:58:05 -080082extern uint8_t tegra_fake_system_suspend;
83
Varun Wadekarb316e242015-05-19 16:48:04 +053084void tegra_pm_system_suspend_entry(void);
85void tegra_pm_system_suspend_exit(void);
86int tegra_system_suspended(void);
87
88/* Declarations for tegraXXX_pm.c */
89int tegra_prepare_cpu_suspend(unsigned int id, unsigned int afflvl);
90int tegra_prepare_cpu_on_finish(unsigned long mpidr);
91
92/* Declarations for tegra_bl31_setup.c */
93plat_params_from_bl2_t *bl31_get_plat_params(void);
Varun Wadekar7a269e22015-06-10 14:04:32 +053094int bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes);
Varun Wadekar3f0a8ad2016-03-28 15:56:47 -070095void plat_early_platform_setup(void);
Varun Wadekarb316e242015-05-19 16:48:04 +053096
Varun Wadekarbc74fec2015-07-16 15:47:03 +053097/* Declarations for tegra_delay_timer.c */
98void tegra_delay_timer_init(void);
99
Varun Wadekar93bed2a2016-03-18 13:07:33 -0700100void tegra_secure_entrypoint(void);
101void tegra186_cpu_reset_handler(void);
102
Varun Wadekarb316e242015-05-19 16:48:04 +0530103#endif /* __TEGRA_PRIVATE_H__ */