Tegra: fix trivial misra issues
Not having U or ULL as a suffix for these enums causes
a lot of unnecessary MISRA issues. This patch adds U or
ULL suffix to these common enums to reduce number of
MISRA issues.
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
diff --git a/plat/nvidia/tegra/include/tegra_private.h b/plat/nvidia/tegra/include/tegra_private.h
index edd1f65..10065db 100644
--- a/plat/nvidia/tegra/include/tegra_private.h
+++ b/plat/nvidia/tegra/include/tegra_private.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -39,8 +39,8 @@
/*******************************************************************************
* Tegra DRAM memory base address
******************************************************************************/
-#define TEGRA_DRAM_BASE 0x80000000
-#define TEGRA_DRAM_END 0x27FFFFFFF
+#define TEGRA_DRAM_BASE 0x80000000ULL
+#define TEGRA_DRAM_END 0x27FFFFFFFULL
/*******************************************************************************
* Struct for parameters received from BL2