Jacky Bai | f7dc401 | 2019-03-06 16:58:18 +0800 | [diff] [blame] | 1 | /* |
Jacky Bai | a940799 | 2020-01-08 16:56:01 +0800 | [diff] [blame^] | 2 | * Copyright (c) 2018-2023, ARM Limited and Contributors. All rights reserved. |
Jacky Bai | f7dc401 | 2019-03-06 16:58:18 +0800 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <stdbool.h> |
| 8 | |
| 9 | #include <arch.h> |
| 10 | #include <arch_helpers.h> |
| 11 | #include <common/debug.h> |
Jacky Bai | 31f0232 | 2019-12-11 16:26:59 +0800 | [diff] [blame] | 12 | #include <common/runtime_svc.h> |
Jacky Bai | f7dc401 | 2019-03-06 16:58:18 +0800 | [diff] [blame] | 13 | #include <lib/mmio.h> |
| 14 | #include <lib/psci/psci.h> |
| 15 | |
| 16 | #include <gpc.h> |
| 17 | #include <imx8m_psci.h> |
| 18 | #include <plat_imx8.h> |
| 19 | |
Jacky Bai | 11261fa | 2019-12-09 13:27:39 +0800 | [diff] [blame] | 20 | #define MAX_PLL_NUM U(10) |
| 21 | |
Jacky Bai | ad81816 | 2020-07-22 16:00:50 +0800 | [diff] [blame] | 22 | static uint32_t gpc_imr_offset[] = { IMR1_CORE0_A53, IMR1_CORE1_A53, IMR1_CORE2_A53, IMR1_CORE3_A53, }; |
Jacky Bai | f7dc401 | 2019-03-06 16:58:18 +0800 | [diff] [blame] | 23 | |
Jacky Bai | 3710fc7 | 2020-01-07 11:05:22 +0800 | [diff] [blame] | 24 | DEFINE_BAKERY_LOCK(gpc_lock); |
| 25 | |
Jacky Bai | 31f0232 | 2019-12-11 16:26:59 +0800 | [diff] [blame] | 26 | #define FSL_SIP_CONFIG_GPC_PM_DOMAIN 0x03 |
| 27 | |
Jacky Bai | f7dc401 | 2019-03-06 16:58:18 +0800 | [diff] [blame] | 28 | #pragma weak imx_set_cpu_pwr_off |
| 29 | #pragma weak imx_set_cpu_pwr_on |
| 30 | #pragma weak imx_set_cpu_lpm |
| 31 | #pragma weak imx_set_cluster_powerdown |
Jacky Bai | a940799 | 2020-01-08 16:56:01 +0800 | [diff] [blame^] | 32 | #pragma weak imx_set_sys_wakeup |
| 33 | #pragma weak imx_noc_slot_config |
| 34 | #pragma weak imx_gpc_handler |
Jacky Bai | f7dc401 | 2019-03-06 16:58:18 +0800 | [diff] [blame] | 35 | |
| 36 | void imx_set_cpu_secure_entry(unsigned int core_id, uintptr_t sec_entrypoint) |
| 37 | { |
| 38 | uint64_t temp_base; |
| 39 | |
| 40 | temp_base = (uint64_t) sec_entrypoint; |
| 41 | temp_base >>= 2; |
| 42 | |
| 43 | mmio_write_32(IMX_SRC_BASE + SRC_GPR1_OFFSET + (core_id << 3), |
| 44 | ((uint32_t)(temp_base >> 22) & 0xffff)); |
| 45 | mmio_write_32(IMX_SRC_BASE + SRC_GPR1_OFFSET + (core_id << 3) + 4, |
| 46 | ((uint32_t)temp_base & 0x003fffff)); |
| 47 | } |
| 48 | |
| 49 | void imx_set_cpu_pwr_off(unsigned int core_id) |
| 50 | { |
Jacky Bai | 3710fc7 | 2020-01-07 11:05:22 +0800 | [diff] [blame] | 51 | |
| 52 | bakery_lock_get(&gpc_lock); |
| 53 | |
Jacky Bai | f7dc401 | 2019-03-06 16:58:18 +0800 | [diff] [blame] | 54 | /* enable the wfi power down of the core */ |
| 55 | mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id)); |
Jacky Bai | 3710fc7 | 2020-01-07 11:05:22 +0800 | [diff] [blame] | 56 | |
| 57 | bakery_lock_release(&gpc_lock); |
| 58 | |
Jacky Bai | f7dc401 | 2019-03-06 16:58:18 +0800 | [diff] [blame] | 59 | /* assert the pcg pcr bit of the core */ |
| 60 | mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); |
| 61 | } |
| 62 | |
| 63 | void imx_set_cpu_pwr_on(unsigned int core_id) |
| 64 | { |
Jacky Bai | 3710fc7 | 2020-01-07 11:05:22 +0800 | [diff] [blame] | 65 | bakery_lock_get(&gpc_lock); |
| 66 | |
Jacky Bai | f7dc401 | 2019-03-06 16:58:18 +0800 | [diff] [blame] | 67 | /* clear the wfi power down bit of the core */ |
| 68 | mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id)); |
Jacky Bai | 3710fc7 | 2020-01-07 11:05:22 +0800 | [diff] [blame] | 69 | |
| 70 | bakery_lock_release(&gpc_lock); |
| 71 | |
Jacky Bai | f7dc401 | 2019-03-06 16:58:18 +0800 | [diff] [blame] | 72 | /* assert the ncpuporeset */ |
| 73 | mmio_clrbits_32(IMX_SRC_BASE + SRC_A53RCR1, (1 << core_id)); |
| 74 | /* assert the pcg pcr bit of the core */ |
| 75 | mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); |
| 76 | /* sw power up the core */ |
| 77 | mmio_setbits_32(IMX_GPC_BASE + CPU_PGC_UP_TRG, (1 << core_id)); |
| 78 | |
| 79 | /* wait for the power up finished */ |
| 80 | while ((mmio_read_32(IMX_GPC_BASE + CPU_PGC_UP_TRG) & (1 << core_id)) != 0) |
| 81 | ; |
| 82 | |
| 83 | /* deassert the pcg pcr bit of the core */ |
| 84 | mmio_clrbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); |
| 85 | /* deassert the ncpuporeset */ |
| 86 | mmio_setbits_32(IMX_SRC_BASE + SRC_A53RCR1, (1 << core_id)); |
| 87 | } |
| 88 | |
| 89 | void imx_set_cpu_lpm(unsigned int core_id, bool pdn) |
| 90 | { |
Jacky Bai | 3710fc7 | 2020-01-07 11:05:22 +0800 | [diff] [blame] | 91 | bakery_lock_get(&gpc_lock); |
| 92 | |
Jacky Bai | f7dc401 | 2019-03-06 16:58:18 +0800 | [diff] [blame] | 93 | if (pdn) { |
| 94 | /* enable the core WFI PDN & IRQ PUP */ |
| 95 | mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id) | |
| 96 | COREx_IRQ_WUP(core_id)); |
| 97 | /* assert the pcg pcr bit of the core */ |
| 98 | mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); |
| 99 | } else { |
| 100 | /* disbale CORE WFI PDN & IRQ PUP */ |
| 101 | mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id) | |
| 102 | COREx_IRQ_WUP(core_id)); |
| 103 | /* deassert the pcg pcr bit of the core */ |
| 104 | mmio_clrbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); |
| 105 | } |
Jacky Bai | 3710fc7 | 2020-01-07 11:05:22 +0800 | [diff] [blame] | 106 | |
| 107 | bakery_lock_release(&gpc_lock); |
Jacky Bai | f7dc401 | 2019-03-06 16:58:18 +0800 | [diff] [blame] | 108 | } |
| 109 | |
| 110 | /* |
| 111 | * the plat and noc can only be power up & down by slot method, |
| 112 | * slot0: plat power down; slot1: noc power down; slot2: noc power up; |
| 113 | * slot3: plat power up. plat's pup&pdn ack is used by default. if |
| 114 | * noc is config to power down, then noc's pdn ack should be used. |
| 115 | */ |
| 116 | static void imx_a53_plat_slot_config(bool pdn) |
| 117 | { |
| 118 | if (pdn) { |
| 119 | mmio_setbits_32(IMX_GPC_BASE + SLTx_CFG(0), PLAT_PDN_SLT_CTRL); |
| 120 | mmio_setbits_32(IMX_GPC_BASE + SLTx_CFG(3), PLAT_PUP_SLT_CTRL); |
| 121 | mmio_write_32(IMX_GPC_BASE + PGC_ACK_SEL_A53, A53_PLAT_PDN_ACK | |
| 122 | A53_PLAT_PUP_ACK); |
| 123 | mmio_setbits_32(IMX_GPC_BASE + PLAT_PGC_PCR, 0x1); |
| 124 | } else { |
| 125 | mmio_clrbits_32(IMX_GPC_BASE + SLTx_CFG(0), PLAT_PDN_SLT_CTRL); |
| 126 | mmio_clrbits_32(IMX_GPC_BASE + SLTx_CFG(3), PLAT_PUP_SLT_CTRL); |
| 127 | mmio_write_32(IMX_GPC_BASE + PGC_ACK_SEL_A53, A53_DUMMY_PUP_ACK | |
| 128 | A53_DUMMY_PDN_ACK); |
| 129 | mmio_clrbits_32(IMX_GPC_BASE + PLAT_PGC_PCR, 0x1); |
| 130 | } |
| 131 | } |
| 132 | |
| 133 | void imx_set_cluster_standby(bool enter) |
| 134 | { |
| 135 | /* |
| 136 | * Enable BIT 6 of A53 AD register to make sure system |
| 137 | * don't enter LPM mode. |
| 138 | */ |
| 139 | if (enter) |
| 140 | mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_AD, (1 << 6)); |
| 141 | else |
| 142 | mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_AD, (1 << 6)); |
| 143 | } |
| 144 | |
| 145 | /* i.mx8mq need to override it */ |
| 146 | void imx_set_cluster_powerdown(unsigned int last_core, uint8_t power_state) |
| 147 | { |
| 148 | uint32_t val; |
| 149 | |
| 150 | if (!is_local_state_run(power_state)) { |
| 151 | /* config C0~1's LPM, enable a53 clock off in LPM */ |
| 152 | mmio_clrsetbits_32(IMX_GPC_BASE + LPCR_A53_BSC, A53_CLK_ON_LPM, |
| 153 | LPM_MODE(power_state)); |
| 154 | /* config C2-3's LPM */ |
| 155 | mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_BSC2, LPM_MODE(power_state)); |
| 156 | |
| 157 | /* enable PLAT/SCU power down */ |
| 158 | val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_AD); |
| 159 | val &= ~EN_L2_WFI_PDN; |
| 160 | /* L2 cache memory is on in WAIT mode */ |
Jacky Bai | 534563e | 2019-12-09 09:53:28 +0800 | [diff] [blame] | 161 | if (is_local_state_off(power_state)) { |
Jacky Bai | f7dc401 | 2019-03-06 16:58:18 +0800 | [diff] [blame] | 162 | val |= (L2PGE | EN_PLAT_PDN); |
Jacky Bai | 534563e | 2019-12-09 09:53:28 +0800 | [diff] [blame] | 163 | imx_a53_plat_slot_config(true); |
| 164 | } |
Jacky Bai | f7dc401 | 2019-03-06 16:58:18 +0800 | [diff] [blame] | 165 | |
| 166 | mmio_write_32(IMX_GPC_BASE + LPCR_A53_AD, val); |
Jacky Bai | f7dc401 | 2019-03-06 16:58:18 +0800 | [diff] [blame] | 167 | } else { |
| 168 | /* clear the slot and ack for cluster power down */ |
| 169 | imx_a53_plat_slot_config(false); |
| 170 | /* reverse the cluster level setting */ |
| 171 | mmio_clrsetbits_32(IMX_GPC_BASE + LPCR_A53_BSC, 0xf, A53_CLK_ON_LPM); |
| 172 | mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_BSC2, 0xf); |
| 173 | |
| 174 | /* clear PLAT/SCU power down */ |
| 175 | mmio_clrsetbits_32(IMX_GPC_BASE + LPCR_A53_AD, (L2PGE | EN_PLAT_PDN), |
| 176 | EN_L2_WFI_PDN); |
| 177 | } |
| 178 | } |
| 179 | |
| 180 | static unsigned int gicd_read_isenabler(uintptr_t base, unsigned int id) |
| 181 | { |
| 182 | unsigned int n = id >> ISENABLER_SHIFT; |
| 183 | |
| 184 | return mmio_read_32(base + GICD_ISENABLER + (n << 2)); |
| 185 | } |
| 186 | |
| 187 | /* |
| 188 | * gic's clock will be gated in system suspend, so gic has no ability to |
| 189 | * to wakeup the system, we need to config the imr based on the irq |
| 190 | * enable status in gic, then gpc will monitor the wakeup irq |
| 191 | */ |
| 192 | void imx_set_sys_wakeup(unsigned int last_core, bool pdn) |
| 193 | { |
| 194 | uint32_t irq_mask; |
| 195 | uintptr_t gicd_base = PLAT_GICD_BASE; |
| 196 | |
| 197 | if (pdn) |
| 198 | mmio_clrsetbits_32(IMX_GPC_BASE + LPCR_A53_BSC, A53_CORE_WUP_SRC(last_core), |
| 199 | IRQ_SRC_A53_WUP); |
| 200 | else |
| 201 | mmio_clrsetbits_32(IMX_GPC_BASE + LPCR_A53_BSC, IRQ_SRC_A53_WUP, |
| 202 | A53_CORE_WUP_SRC(last_core)); |
| 203 | |
| 204 | /* clear last core's IMR based on GIC's mask setting */ |
| 205 | for (int i = 0; i < IRQ_IMR_NUM; i++) { |
| 206 | if (pdn) |
| 207 | /* set the wakeup irq base GIC */ |
| 208 | irq_mask = ~gicd_read_isenabler(gicd_base, 32 * (i + 1)); |
| 209 | else |
| 210 | irq_mask = IMR_MASK_ALL; |
| 211 | |
| 212 | mmio_write_32(IMX_GPC_BASE + gpc_imr_offset[last_core] + i * 4, |
| 213 | irq_mask); |
| 214 | } |
| 215 | } |
| 216 | |
Jacky Bai | f7dc401 | 2019-03-06 16:58:18 +0800 | [diff] [blame] | 217 | /* |
| 218 | * this function only need to be override by platform |
| 219 | * that support noc power down, for example: imx8mm. |
| 220 | * otherwize, keep it empty. |
| 221 | */ |
| 222 | void imx_noc_slot_config(bool pdn) |
| 223 | { |
| 224 | |
| 225 | } |
| 226 | |
| 227 | /* this is common for all imx8m soc */ |
| 228 | void imx_set_sys_lpm(unsigned int last_core, bool retention) |
| 229 | { |
| 230 | uint32_t val; |
| 231 | |
| 232 | val = mmio_read_32(IMX_GPC_BASE + SLPCR); |
| 233 | val &= ~(SLPCR_EN_DSM | SLPCR_VSTBY | SLPCR_SBYOS | |
| 234 | SLPCR_BYPASS_PMIC_READY | SLPCR_A53_FASTWUP_STOP_MODE); |
| 235 | |
| 236 | if (retention) |
| 237 | val |= (SLPCR_EN_DSM | SLPCR_VSTBY | SLPCR_SBYOS | |
| 238 | SLPCR_BYPASS_PMIC_READY | SLPCR_A53_FASTWUP_STOP_MODE); |
| 239 | |
| 240 | mmio_write_32(IMX_GPC_BASE + SLPCR, val); |
| 241 | |
| 242 | /* config the noc power down */ |
| 243 | imx_noc_slot_config(retention); |
| 244 | |
| 245 | /* config wakeup irqs' mask in gpc */ |
| 246 | imx_set_sys_wakeup(last_core, retention); |
| 247 | } |
| 248 | |
| 249 | void imx_set_rbc_count(void) |
| 250 | { |
| 251 | mmio_setbits_32(IMX_GPC_BASE + SLPCR, SLPCR_RBC_EN | |
| 252 | (0x8 << SLPCR_RBC_COUNT_SHIFT)); |
| 253 | } |
| 254 | |
| 255 | void imx_clear_rbc_count(void) |
| 256 | { |
| 257 | mmio_clrbits_32(IMX_GPC_BASE + SLPCR, SLPCR_RBC_EN | |
| 258 | (0x3f << SLPCR_RBC_COUNT_SHIFT)); |
| 259 | } |
Jacky Bai | 11261fa | 2019-12-09 13:27:39 +0800 | [diff] [blame] | 260 | |
| 261 | struct pll_override { |
| 262 | uint32_t reg; |
| 263 | uint32_t override_mask; |
| 264 | }; |
| 265 | |
| 266 | struct pll_override pll[MAX_PLL_NUM] = { |
| 267 | {.reg = 0x0, .override_mask = (1 << 12) | (1 << 8), }, |
| 268 | {.reg = 0x14, .override_mask = (1 << 12) | (1 << 8), }, |
| 269 | {.reg = 0x28, .override_mask = (1 << 12) | (1 << 8), }, |
| 270 | {.reg = 0x50, .override_mask = (1 << 12) | (1 << 8), }, |
| 271 | {.reg = 0x64, .override_mask = (1 << 10) | (1 << 8), }, |
| 272 | {.reg = 0x74, .override_mask = (1 << 10) | (1 << 8), }, |
| 273 | {.reg = 0x84, .override_mask = (1 << 10) | (1 << 8), }, |
| 274 | {.reg = 0x94, .override_mask = 0x5555500, }, |
| 275 | {.reg = 0x104, .override_mask = 0x5555500, }, |
| 276 | {.reg = 0x114, .override_mask = 0x500, }, |
| 277 | }; |
| 278 | |
| 279 | #define PLL_BYPASS BIT(4) |
| 280 | void imx_anamix_override(bool enter) |
| 281 | { |
| 282 | unsigned int i; |
| 283 | |
| 284 | /* |
| 285 | * bypass all the plls & enable the override bit before |
| 286 | * entering DSM mode. |
| 287 | */ |
| 288 | for (i = 0U; i < MAX_PLL_NUM; i++) { |
| 289 | if (enter) { |
| 290 | mmio_setbits_32(IMX_ANAMIX_BASE + pll[i].reg, PLL_BYPASS); |
| 291 | mmio_setbits_32(IMX_ANAMIX_BASE + pll[i].reg, pll[i].override_mask); |
| 292 | } else { |
| 293 | mmio_clrbits_32(IMX_ANAMIX_BASE + pll[i].reg, PLL_BYPASS); |
| 294 | mmio_clrbits_32(IMX_ANAMIX_BASE + pll[i].reg, pll[i].override_mask); |
| 295 | } |
| 296 | } |
Jacky Bai | 31f0232 | 2019-12-11 16:26:59 +0800 | [diff] [blame] | 297 | } |
| 298 | |
| 299 | int imx_gpc_handler(uint32_t smc_fid, u_register_t x1, u_register_t x2, u_register_t x3) |
| 300 | { |
| 301 | switch (x1) { |
| 302 | case FSL_SIP_CONFIG_GPC_PM_DOMAIN: |
| 303 | imx_gpc_pm_domain_enable(x2, x3); |
| 304 | break; |
| 305 | default: |
| 306 | return SMC_UNK; |
| 307 | } |
| 308 | |
| 309 | return 0; |
Jacky Bai | 11261fa | 2019-12-09 13:27:39 +0800 | [diff] [blame] | 310 | } |