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Jeenu Viswambharane86a2472018-07-05 15:24:45 +01001/*
Antonio Nino Diaz594811b2019-01-31 11:58:00 +00002 * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
Jeenu Viswambharane86a2472018-07-05 15:24:45 +01003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7
Jeenu Viswambharan93bc4bd2018-05-17 11:24:01 +01008#include <assert_macros.S>
Jeenu Viswambharane86a2472018-07-05 15:24:45 +01009#include <asm_macros.S>
Jeenu Viswambharan476c29f2018-02-19 12:25:53 +000010#include <assert_macros.S>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011#include <bl31/ea_handle.h>
Jeenu Viswambharane86a2472018-07-05 15:24:45 +010012#include <context.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000013#include <lib/extensions/ras_arch.h>
laurenw-arm94accd32019-08-20 15:51:24 -050014#include <cpu_macros.S>
15#include <context.h>
Jeenu Viswambharane86a2472018-07-05 15:24:45 +010016
17 .globl handle_lower_el_ea_esb
18 .globl enter_lower_el_sync_ea
19 .globl enter_lower_el_async_ea
20
21
22/*
23 * Function to delegate External Aborts synchronized by ESB instruction at EL3
24 * vector entry. This function assumes GP registers x0-x29 have been saved, and
25 * are available for use. It delegates the handling of the EA to platform
26 * handler, and returns only upon successfully handling the EA; otherwise
27 * panics. On return from this function, the original exception handler is
28 * expected to resume.
29 */
30func handle_lower_el_ea_esb
31 mov x0, #ERROR_EA_ESB
32 mrs x1, DISR_EL1
33 b ea_proceed
34endfunc handle_lower_el_ea_esb
35
36
37/*
38 * This function forms the tail end of Synchronous Exception entry from lower
laurenw-arm94accd32019-08-20 15:51:24 -050039 * EL, and expects to handle Synchronous External Aborts from lower EL and CPU
40 * Implementation Defined Exceptions. If any other kind of exception is detected,
41 * then this function reports unhandled exception.
Jeenu Viswambharane86a2472018-07-05 15:24:45 +010042 *
43 * Since it's part of exception vector, this function doesn't expect any GP
44 * registers to have been saved. It delegates the handling of the EA to platform
45 * handler, and upon successfully handling the EA, exits EL3; otherwise panics.
46 */
47func enter_lower_el_sync_ea
48 /*
49 * Explicitly save x30 so as to free up a register and to enable
50 * branching.
51 */
52 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
53
54 mrs x30, esr_el3
55 ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH
56
57 /* Check for I/D aborts from lower EL */
58 cmp x30, #EC_IABORT_LOWER_EL
59 b.eq 1f
60
61 cmp x30, #EC_DABORT_LOWER_EL
laurenw-arm94accd32019-08-20 15:51:24 -050062 b.eq 1f
63
64 /* Save GP registers */
65 stp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
66 stp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
67 stp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
68
69 /* Get the cpu_ops pointer */
70 bl get_cpu_ops_ptr
71
72 /* Get the cpu_ops exception handler */
73 ldr x0, [x0, #CPU_E_HANDLER_FUNC]
74
75 /*
76 * If the reserved function pointer is NULL, this CPU does not have an
77 * implementation defined exception handler function
78 */
79 cbz x0, 2f
80 mrs x1, esr_el3
81 ubfx x1, x1, #ESR_EC_SHIFT, #ESR_EC_LENGTH
82 blr x0
83 b 2f
Jeenu Viswambharane86a2472018-07-05 15:24:45 +010084
851:
86 /* Test for EA bit in the instruction syndrome */
87 mrs x30, esr_el3
laurenw-arm94accd32019-08-20 15:51:24 -050088 tbz x30, #ESR_ISS_EABORT_EA_BIT, 3f
Jeenu Viswambharane86a2472018-07-05 15:24:45 +010089
Alexei Fedorov503bbf32019-08-13 15:17:53 +010090 /*
Alexei Fedorovf41355c2019-09-13 14:11:59 +010091 * Save general purpose and ARMv8.3-PAuth registers (if enabled).
92 * If Secure Cycle Counter is not disabled in MDCR_EL3 when
93 * ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter.
Alexei Fedorov503bbf32019-08-13 15:17:53 +010094 */
Alexei Fedorovf41355c2019-09-13 14:11:59 +010095 bl save_gp_pmcr_pauth_regs
Alexei Fedorov503bbf32019-08-13 15:17:53 +010096
Antonio Nino Diaz25cda672019-02-19 11:53:51 +000097#if ENABLE_PAUTH
Alexei Fedorovf41355c2019-09-13 14:11:59 +010098 /* Load and program APIAKey firmware key */
99 bl pauth_load_bl31_apiakey
Antonio Nino Diaz25cda672019-02-19 11:53:51 +0000100#endif
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000101
Jeenu Viswambharane86a2472018-07-05 15:24:45 +0100102 /* Setup exception class and syndrome arguments for platform handler */
103 mov x0, #ERROR_EA_SYNC
104 mrs x1, esr_el3
Jan Dabrosfa015982019-12-02 13:30:03 +0100105 bl delegate_sync_ea
Jeenu Viswambharane86a2472018-07-05 15:24:45 +0100106
Jan Dabrosfa015982019-12-02 13:30:03 +0100107 /* el3_exit assumes SP_EL0 on entry */
108 msr spsel, #MODE_SP_EL0
109 b el3_exit
Jeenu Viswambharane86a2472018-07-05 15:24:45 +01001102:
laurenw-arm94accd32019-08-20 15:51:24 -0500111 ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
112 ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
113 ldp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
114
1153:
Jeenu Viswambharane86a2472018-07-05 15:24:45 +0100116 /* Synchronous exceptions other than the above are assumed to be EA */
117 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
118 no_ret report_unhandled_exception
119endfunc enter_lower_el_sync_ea
120
121
122/*
123 * This function handles SErrors from lower ELs.
124 *
125 * Since it's part of exception vector, this function doesn't expect any GP
126 * registers to have been saved. It delegates the handling of the EA to platform
127 * handler, and upon successfully handling the EA, exits EL3; otherwise panics.
128 */
129func enter_lower_el_async_ea
130 /*
131 * Explicitly save x30 so as to free up a register and to enable
132 * branching
133 */
134 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
135
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100136 /*
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100137 * Save general purpose and ARMv8.3-PAuth registers (if enabled).
138 * If Secure Cycle Counter is not disabled in MDCR_EL3 when
139 * ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter.
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100140 */
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100141 bl save_gp_pmcr_pauth_regs
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100142
Antonio Nino Diaz25cda672019-02-19 11:53:51 +0000143#if ENABLE_PAUTH
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100144 /* Load and program APIAKey firmware key */
145 bl pauth_load_bl31_apiakey
Antonio Nino Diaz25cda672019-02-19 11:53:51 +0000146#endif
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000147
Jeenu Viswambharane86a2472018-07-05 15:24:45 +0100148 /* Setup exception class and syndrome arguments for platform handler */
149 mov x0, #ERROR_EA_ASYNC
150 mrs x1, esr_el3
Jan Dabrosfa015982019-12-02 13:30:03 +0100151 bl delegate_async_ea
152
153 /* el3_exit assumes SP_EL0 on entry */
154 msr spsel, #MODE_SP_EL0
155 b el3_exit
Jeenu Viswambharane86a2472018-07-05 15:24:45 +0100156endfunc enter_lower_el_async_ea
157
158
159/*
Jeenu Viswambharan9d4c9c12018-05-17 09:52:36 +0100160 * Prelude for Synchronous External Abort handling. This function assumes that
161 * all GP registers have been saved by the caller.
162 *
163 * x0: EA reason
164 * x1: EA syndrome
165 */
166func delegate_sync_ea
167#if RAS_EXTENSION
168 /*
169 * Check for Uncontainable error type. If so, route to the platform
170 * fatal error handler rather than the generic EA one.
171 */
172 ubfx x2, x1, #EABORT_SET_SHIFT, #EABORT_SET_WIDTH
173 cmp x2, #ERROR_STATUS_SET_UC
174 b.ne 1f
175
176 /* Check fault status code */
177 ubfx x3, x1, #EABORT_DFSC_SHIFT, #EABORT_DFSC_WIDTH
178 cmp x3, #SYNC_EA_FSC
179 b.ne 1f
180
181 no_ret plat_handle_uncontainable_ea
1821:
183#endif
184
185 b ea_proceed
186endfunc delegate_sync_ea
187
188
189/*
190 * Prelude for Asynchronous External Abort handling. This function assumes that
191 * all GP registers have been saved by the caller.
192 *
193 * x0: EA reason
194 * x1: EA syndrome
195 */
196func delegate_async_ea
197#if RAS_EXTENSION
198 /*
199 * Check for Implementation Defined Syndrome. If so, skip checking
200 * Uncontainable error type from the syndrome as the format is unknown.
201 */
202 tbnz x1, #SERROR_IDS_BIT, 1f
203
204 /*
205 * Check for Uncontainable error type. If so, route to the platform
206 * fatal error handler rather than the generic EA one.
207 */
208 ubfx x2, x1, #EABORT_AET_SHIFT, #EABORT_AET_WIDTH
209 cmp x2, #ERROR_STATUS_UET_UC
210 b.ne 1f
211
212 /* Check DFSC for SError type */
213 ubfx x3, x1, #EABORT_DFSC_SHIFT, #EABORT_DFSC_WIDTH
214 cmp x3, #DFSC_SERROR
215 b.ne 1f
216
217 no_ret plat_handle_uncontainable_ea
2181:
219#endif
220
221 b ea_proceed
222endfunc delegate_async_ea
223
224
225/*
Jeenu Viswambharane86a2472018-07-05 15:24:45 +0100226 * Delegate External Abort handling to platform's EA handler. This function
227 * assumes that all GP registers have been saved by the caller.
228 *
229 * x0: EA reason
230 * x1: EA syndrome
231 */
232func ea_proceed
Jeenu Viswambharan93bc4bd2018-05-17 11:24:01 +0100233 /*
234 * If the ESR loaded earlier is not zero, we were processing an EA
235 * already, and this is a double fault.
236 */
237 ldr x5, [sp, #CTX_EL3STATE_OFFSET + CTX_ESR_EL3]
238 cbz x5, 1f
239 no_ret plat_handle_double_fault
240
2411:
Jeenu Viswambharane86a2472018-07-05 15:24:45 +0100242 /* Save EL3 state */
243 mrs x2, spsr_el3
244 mrs x3, elr_el3
245 stp x2, x3, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
246
247 /*
248 * Save ESR as handling might involve lower ELs, and returning back to
249 * EL3 from there would trample the original ESR.
250 */
251 mrs x4, scr_el3
252 mrs x5, esr_el3
253 stp x4, x5, [sp, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3]
254
255 /*
256 * Setup rest of arguments, and call platform External Abort handler.
257 *
258 * x0: EA reason (already in place)
259 * x1: Exception syndrome (already in place).
260 * x2: Cookie (unused for now).
261 * x3: Context pointer.
262 * x4: Flags (security state from SCR for now).
263 */
264 mov x2, xzr
265 mov x3, sp
266 ubfx x4, x4, #0, #1
267
268 /* Switch to runtime stack */
269 ldr x5, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP]
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100270 msr spsel, #MODE_SP_EL0
Jeenu Viswambharane86a2472018-07-05 15:24:45 +0100271 mov sp, x5
272
273 mov x29, x30
Jeenu Viswambharan476c29f2018-02-19 12:25:53 +0000274#if ENABLE_ASSERTIONS
275 /* Stash the stack pointer */
276 mov x28, sp
277#endif
Jeenu Viswambharane86a2472018-07-05 15:24:45 +0100278 bl plat_ea_handler
Jeenu Viswambharane86a2472018-07-05 15:24:45 +0100279
Jeenu Viswambharan476c29f2018-02-19 12:25:53 +0000280#if ENABLE_ASSERTIONS
281 /*
282 * Error handling flows might involve long jumps; so upon returning from
283 * the platform error handler, validate that the we've completely
284 * unwound the stack.
285 */
286 mov x27, sp
287 cmp x28, x27
288 ASM_ASSERT(eq)
289#endif
290
Jeenu Viswambharane86a2472018-07-05 15:24:45 +0100291 /* Make SP point to context */
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100292 msr spsel, #MODE_SP_ELX
Jeenu Viswambharane86a2472018-07-05 15:24:45 +0100293
Jeenu Viswambharan93bc4bd2018-05-17 11:24:01 +0100294 /* Restore EL3 state and ESR */
Jeenu Viswambharane86a2472018-07-05 15:24:45 +0100295 ldp x1, x2, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
296 msr spsr_el3, x1
297 msr elr_el3, x2
298
299 /* Restore ESR_EL3 and SCR_EL3 */
300 ldp x3, x4, [sp, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3]
301 msr scr_el3, x3
302 msr esr_el3, x4
303
Jeenu Viswambharan93bc4bd2018-05-17 11:24:01 +0100304#if ENABLE_ASSERTIONS
305 cmp x4, xzr
306 ASM_ASSERT(ne)
307#endif
308
309 /* Clear ESR storage */
310 str xzr, [sp, #CTX_EL3STATE_OFFSET + CTX_ESR_EL3]
311
312 ret x29
Jeenu Viswambharane86a2472018-07-05 15:24:45 +0100313endfunc ea_proceed