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Jeenu Viswambharane86a2472018-07-05 15:24:45 +01001/*
Antonio Nino Diaz594811b2019-01-31 11:58:00 +00002 * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
Jeenu Viswambharane86a2472018-07-05 15:24:45 +01003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7
Jeenu Viswambharan93bc4bd2018-05-17 11:24:01 +01008#include <assert_macros.S>
Jeenu Viswambharane86a2472018-07-05 15:24:45 +01009#include <asm_macros.S>
Jeenu Viswambharan476c29f2018-02-19 12:25:53 +000010#include <assert_macros.S>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011#include <bl31/ea_handle.h>
Jeenu Viswambharane86a2472018-07-05 15:24:45 +010012#include <context.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000013#include <lib/extensions/ras_arch.h>
Jeenu Viswambharane86a2472018-07-05 15:24:45 +010014
15
16 .globl handle_lower_el_ea_esb
17 .globl enter_lower_el_sync_ea
18 .globl enter_lower_el_async_ea
19
20
21/*
22 * Function to delegate External Aborts synchronized by ESB instruction at EL3
23 * vector entry. This function assumes GP registers x0-x29 have been saved, and
24 * are available for use. It delegates the handling of the EA to platform
25 * handler, and returns only upon successfully handling the EA; otherwise
26 * panics. On return from this function, the original exception handler is
27 * expected to resume.
28 */
29func handle_lower_el_ea_esb
30 mov x0, #ERROR_EA_ESB
31 mrs x1, DISR_EL1
32 b ea_proceed
33endfunc handle_lower_el_ea_esb
34
35
36/*
37 * This function forms the tail end of Synchronous Exception entry from lower
38 * EL, and expects to handle only Synchronous External Aborts from lower EL. If
39 * any other kind of exception is detected, then this function reports unhandled
40 * exception.
41 *
42 * Since it's part of exception vector, this function doesn't expect any GP
43 * registers to have been saved. It delegates the handling of the EA to platform
44 * handler, and upon successfully handling the EA, exits EL3; otherwise panics.
45 */
46func enter_lower_el_sync_ea
47 /*
48 * Explicitly save x30 so as to free up a register and to enable
49 * branching.
50 */
51 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
52
53 mrs x30, esr_el3
54 ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH
55
56 /* Check for I/D aborts from lower EL */
57 cmp x30, #EC_IABORT_LOWER_EL
58 b.eq 1f
59
60 cmp x30, #EC_DABORT_LOWER_EL
61 b.ne 2f
62
631:
64 /* Test for EA bit in the instruction syndrome */
65 mrs x30, esr_el3
66 tbz x30, #ESR_ISS_EABORT_EA_BIT, 2f
67
68 /* Save GP registers */
69 bl save_gp_registers
70
Antonio Nino Diaz594811b2019-01-31 11:58:00 +000071#if CTX_INCLUDE_PAUTH_REGS
72 bl pauth_context_save
73#endif
74
Jeenu Viswambharane86a2472018-07-05 15:24:45 +010075 /* Setup exception class and syndrome arguments for platform handler */
76 mov x0, #ERROR_EA_SYNC
77 mrs x1, esr_el3
78 adr x30, el3_exit
Jeenu Viswambharan9d4c9c12018-05-17 09:52:36 +010079 b delegate_sync_ea
Jeenu Viswambharane86a2472018-07-05 15:24:45 +010080
812:
82 /* Synchronous exceptions other than the above are assumed to be EA */
83 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
84 no_ret report_unhandled_exception
85endfunc enter_lower_el_sync_ea
86
87
88/*
89 * This function handles SErrors from lower ELs.
90 *
91 * Since it's part of exception vector, this function doesn't expect any GP
92 * registers to have been saved. It delegates the handling of the EA to platform
93 * handler, and upon successfully handling the EA, exits EL3; otherwise panics.
94 */
95func enter_lower_el_async_ea
96 /*
97 * Explicitly save x30 so as to free up a register and to enable
98 * branching
99 */
100 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
101
102 /* Save GP registers */
103 bl save_gp_registers
104
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000105#if CTX_INCLUDE_PAUTH_REGS
106 bl pauth_context_save
107#endif
108
Jeenu Viswambharane86a2472018-07-05 15:24:45 +0100109 /* Setup exception class and syndrome arguments for platform handler */
110 mov x0, #ERROR_EA_ASYNC
111 mrs x1, esr_el3
112 adr x30, el3_exit
Jeenu Viswambharan9d4c9c12018-05-17 09:52:36 +0100113 b delegate_async_ea
Jeenu Viswambharane86a2472018-07-05 15:24:45 +0100114endfunc enter_lower_el_async_ea
115
116
117/*
Jeenu Viswambharan9d4c9c12018-05-17 09:52:36 +0100118 * Prelude for Synchronous External Abort handling. This function assumes that
119 * all GP registers have been saved by the caller.
120 *
121 * x0: EA reason
122 * x1: EA syndrome
123 */
124func delegate_sync_ea
125#if RAS_EXTENSION
126 /*
127 * Check for Uncontainable error type. If so, route to the platform
128 * fatal error handler rather than the generic EA one.
129 */
130 ubfx x2, x1, #EABORT_SET_SHIFT, #EABORT_SET_WIDTH
131 cmp x2, #ERROR_STATUS_SET_UC
132 b.ne 1f
133
134 /* Check fault status code */
135 ubfx x3, x1, #EABORT_DFSC_SHIFT, #EABORT_DFSC_WIDTH
136 cmp x3, #SYNC_EA_FSC
137 b.ne 1f
138
139 no_ret plat_handle_uncontainable_ea
1401:
141#endif
142
143 b ea_proceed
144endfunc delegate_sync_ea
145
146
147/*
148 * Prelude for Asynchronous External Abort handling. This function assumes that
149 * all GP registers have been saved by the caller.
150 *
151 * x0: EA reason
152 * x1: EA syndrome
153 */
154func delegate_async_ea
155#if RAS_EXTENSION
156 /*
157 * Check for Implementation Defined Syndrome. If so, skip checking
158 * Uncontainable error type from the syndrome as the format is unknown.
159 */
160 tbnz x1, #SERROR_IDS_BIT, 1f
161
162 /*
163 * Check for Uncontainable error type. If so, route to the platform
164 * fatal error handler rather than the generic EA one.
165 */
166 ubfx x2, x1, #EABORT_AET_SHIFT, #EABORT_AET_WIDTH
167 cmp x2, #ERROR_STATUS_UET_UC
168 b.ne 1f
169
170 /* Check DFSC for SError type */
171 ubfx x3, x1, #EABORT_DFSC_SHIFT, #EABORT_DFSC_WIDTH
172 cmp x3, #DFSC_SERROR
173 b.ne 1f
174
175 no_ret plat_handle_uncontainable_ea
1761:
177#endif
178
179 b ea_proceed
180endfunc delegate_async_ea
181
182
183/*
Jeenu Viswambharane86a2472018-07-05 15:24:45 +0100184 * Delegate External Abort handling to platform's EA handler. This function
185 * assumes that all GP registers have been saved by the caller.
186 *
187 * x0: EA reason
188 * x1: EA syndrome
189 */
190func ea_proceed
Jeenu Viswambharan93bc4bd2018-05-17 11:24:01 +0100191 /*
192 * If the ESR loaded earlier is not zero, we were processing an EA
193 * already, and this is a double fault.
194 */
195 ldr x5, [sp, #CTX_EL3STATE_OFFSET + CTX_ESR_EL3]
196 cbz x5, 1f
197 no_ret plat_handle_double_fault
198
1991:
Jeenu Viswambharane86a2472018-07-05 15:24:45 +0100200 /* Save EL3 state */
201 mrs x2, spsr_el3
202 mrs x3, elr_el3
203 stp x2, x3, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
204
205 /*
206 * Save ESR as handling might involve lower ELs, and returning back to
207 * EL3 from there would trample the original ESR.
208 */
209 mrs x4, scr_el3
210 mrs x5, esr_el3
211 stp x4, x5, [sp, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3]
212
213 /*
214 * Setup rest of arguments, and call platform External Abort handler.
215 *
216 * x0: EA reason (already in place)
217 * x1: Exception syndrome (already in place).
218 * x2: Cookie (unused for now).
219 * x3: Context pointer.
220 * x4: Flags (security state from SCR for now).
221 */
222 mov x2, xzr
223 mov x3, sp
224 ubfx x4, x4, #0, #1
225
226 /* Switch to runtime stack */
227 ldr x5, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP]
228 msr spsel, #0
229 mov sp, x5
230
231 mov x29, x30
Jeenu Viswambharan476c29f2018-02-19 12:25:53 +0000232#if ENABLE_ASSERTIONS
233 /* Stash the stack pointer */
234 mov x28, sp
235#endif
Jeenu Viswambharane86a2472018-07-05 15:24:45 +0100236 bl plat_ea_handler
Jeenu Viswambharane86a2472018-07-05 15:24:45 +0100237
Jeenu Viswambharan476c29f2018-02-19 12:25:53 +0000238#if ENABLE_ASSERTIONS
239 /*
240 * Error handling flows might involve long jumps; so upon returning from
241 * the platform error handler, validate that the we've completely
242 * unwound the stack.
243 */
244 mov x27, sp
245 cmp x28, x27
246 ASM_ASSERT(eq)
247#endif
248
Jeenu Viswambharane86a2472018-07-05 15:24:45 +0100249 /* Make SP point to context */
250 msr spsel, #1
251
Jeenu Viswambharan93bc4bd2018-05-17 11:24:01 +0100252 /* Restore EL3 state and ESR */
Jeenu Viswambharane86a2472018-07-05 15:24:45 +0100253 ldp x1, x2, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
254 msr spsr_el3, x1
255 msr elr_el3, x2
256
257 /* Restore ESR_EL3 and SCR_EL3 */
258 ldp x3, x4, [sp, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3]
259 msr scr_el3, x3
260 msr esr_el3, x4
261
Jeenu Viswambharan93bc4bd2018-05-17 11:24:01 +0100262#if ENABLE_ASSERTIONS
263 cmp x4, xzr
264 ASM_ASSERT(ne)
265#endif
266
267 /* Clear ESR storage */
268 str xzr, [sp, #CTX_EL3STATE_OFFSET + CTX_ESR_EL3]
269
270 ret x29
Jeenu Viswambharane86a2472018-07-05 15:24:45 +0100271endfunc ea_proceed