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git01.mediatek.com / filogic / atf / a7fec062bfb19b11f45a852e5145c7fa7679485a / . / plat / arm / board / rdv1mc / platform.mk
blob: 176e0efff995ab3487783dac6a0185b4a03eb569 [file] [log] [blame]
Aditya Angadiac0e0d32021-02-17 18:46:22 +0530[diff] [blame]1# Copyright (c) 2020-2021, ARM Limited and Contributors. All rights reserved.
Aditya Angadicdd7f632020-04-06 17:11:23 +0530[diff] [blame]2#
3# SPDX-License-Identifier: BSD-3-Clause
4#
5
6# Enable GICv4 extension with multichip driver
7GIC_ENABLE_V4_EXTN := 1
8GICV3_IMPL_GIC600_MULTICHIP := 1
9
10include plat/arm/css/sgi/sgi-common.mk
11
Aditya Angadif5039032020-12-15 17:28:08 +0530[diff] [blame]12RDV1MC_BASE = plat/arm/board/rdv1mc
Aditya Angadicdd7f632020-04-06 17:11:23 +0530[diff] [blame]13
Aditya Angadif5039032020-12-15 17:28:08 +0530[diff] [blame]14PLAT_INCLUDES += -I${RDV1MC_BASE}/include/
Aditya Angadicdd7f632020-04-06 17:11:23 +0530[diff] [blame]15
Jimmy Brisson958a0b12020-09-30 15:28:03 -0500[diff] [blame]16SGI_CPU_SOURCES := lib/cpus/aarch64/neoverse_v1.S
Aditya Angadicdd7f632020-04-06 17:11:23 +0530[diff] [blame]17
Aditya Angadi502d0ac2020-11-18 08:27:15 +0530[diff] [blame]18PLAT_BL_COMMON_SOURCES += ${CSS_ENT_BASE}/sgi_plat.c
19
Aditya Angadicdd7f632020-04-06 17:11:23 +0530[diff] [blame]20BL1_SOURCES += ${SGI_CPU_SOURCES} \
Aditya Angadif5039032020-12-15 17:28:08 +0530[diff] [blame]21 ${RDV1MC_BASE}/rdv1mc_err.c
Aditya Angadicdd7f632020-04-06 17:11:23 +0530[diff] [blame]22
Aditya Angadif5039032020-12-15 17:28:08 +0530[diff] [blame]23BL2_SOURCES += ${RDV1MC_BASE}/rdv1mc_plat.c \
24 ${RDV1MC_BASE}/rdv1mc_security.c \
25 ${RDV1MC_BASE}/rdv1mc_err.c \
Aditya Angadiac0e0d32021-02-17 18:46:22 +0530[diff] [blame]26 drivers/arm/tzc/tzc400.c \
27 plat/arm/common/arm_tzc400.c \
Aditya Angadicdd7f632020-04-06 17:11:23 +0530[diff] [blame]28 lib/utils/mem_region.c \
29 plat/arm/common/arm_nor_psci_mem_protect.c
30
31BL31_SOURCES += ${SGI_CPU_SOURCES} \
Aditya Angadif5039032020-12-15 17:28:08 +0530[diff] [blame]32 ${RDV1MC_BASE}/rdv1mc_plat.c \
33 ${RDV1MC_BASE}/rdv1mc_topology.c \
Aditya Angadicdd7f632020-04-06 17:11:23 +0530[diff] [blame]34 drivers/cfi/v2m/v2m_flash.c \
35 drivers/arm/gic/v3/gic600_multichip.c \
36 lib/utils/mem_region.c \
37 plat/arm/common/arm_nor_psci_mem_protect.c
38
Vijayenthiran Subramaniam01ce6fe2020-07-14 15:51:37 +0530[diff] [blame]39ifeq (${TRUSTED_BOARD_BOOT}, 1)
Aditya Angadif5039032020-12-15 17:28:08 +0530[diff] [blame]40BL1_SOURCES += ${RDV1MC_BASE}/rdv1mc_trusted_boot.c
41BL2_SOURCES += ${RDV1MC_BASE}/rdv1mc_trusted_boot.c
Vijayenthiran Subramaniam01ce6fe2020-07-14 15:51:37 +0530[diff] [blame]42endif
43
Aditya Angadicdd7f632020-04-06 17:11:23 +0530[diff] [blame]44# Enable dynamic addition of MMAP regions in BL31
45BL31_CFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC
46
47# Add the FDT_SOURCES and options for Dynamic Config
Aditya Angadif5039032020-12-15 17:28:08 +0530[diff] [blame]48FDT_SOURCES += ${RDV1MC_BASE}/fdts/${PLAT}_fw_config.dts \
49 ${RDV1MC_BASE}/fdts/${PLAT}_tb_fw_config.dts
Manish V Badarkhe64616a52020-05-31 08:53:40 +0100[diff] [blame]50FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb
51TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb
Aditya Angadicdd7f632020-04-06 17:11:23 +0530[diff] [blame]52
Manish V Badarkhe64616a52020-05-31 08:53:40 +0100[diff] [blame]53# Add the FW_CONFIG to FIP and specify the same to certtool
Anders Dellien3f694742020-08-23 19:32:48 +0100[diff] [blame]54$(eval $(call TOOL_ADD_PAYLOAD,${FW_CONFIG},--fw-config,${FW_CONFIG}))
Aditya Angadicdd7f632020-04-06 17:11:23 +0530[diff] [blame]55# Add the TB_FW_CONFIG to FIP and specify the same to certtool
Anders Dellien3f694742020-08-23 19:32:48 +0100[diff] [blame]56$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config,${TB_FW_CONFIG}))
Aditya Angadicdd7f632020-04-06 17:11:23 +0530[diff] [blame]57
58$(eval $(call CREATE_SEQ,SEQ,4))
59ifneq ($(CSS_SGI_CHIP_COUNT),$(filter $(CSS_SGI_CHIP_COUNT),$(SEQ)))
Aditya Angadif5039032020-12-15 17:28:08 +0530[diff] [blame]60 $(error "Chip count for RD-V1-MC should be either $(SEQ) \
Aditya Angadicdd7f632020-04-06 17:11:23 +0530[diff] [blame]61 currently it is set to ${CSS_SGI_CHIP_COUNT}.")
62endif
63
Aditya Angadif5039032020-12-15 17:28:08 +0530[diff] [blame]64FDT_SOURCES += ${RDV1MC_BASE}/fdts/${PLAT}_nt_fw_config.dts
Aditya Angadicdd7f632020-04-06 17:11:23 +0530[diff] [blame]65NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb
66
67# Add the NT_FW_CONFIG to FIP and specify the same to certtool
Anders Dellien3f694742020-08-23 19:32:48 +0100[diff] [blame]68$(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config,${NT_FW_CONFIG}))
Aditya Angadicdd7f632020-04-06 17:11:23 +0530[diff] [blame]69
70override CTX_INCLUDE_AARCH32_REGS := 0
Andre Przywara0b7f1b02023-03-21 13:53:19 +0000[diff] [blame]71override ENABLE_FEAT_AMU := 1
Aditya Angadi06402222021-03-20 12:06:15 +0530[diff] [blame]72
73ifneq ($(CSS_SGI_PLATFORM_VARIANT),0)
74 $(error "CSS_SGI_PLATFORM_VARIANT for RD-V1-MC should always be 0, \
75 currently set to ${CSS_SGI_PLATFORM_VARIANT}.")
76endif
Nuno Lopes8f3bd472023-11-28 12:19:24 +0000[diff] [blame]77
78# Enable the flag since RD-V1-MC has a system level cache
79NEOVERSE_Nx_EXTERNAL_LLC := 1