Jit Loon Lim | a7f5494 | 2023-05-17 12:26:11 +0800 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (c) 2022-2023, Intel Corporation. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef CDN_COMBOPHY_H |
| 8 | #define CDN_COMBOPHY_H |
| 9 | |
| 10 | /* SRS */ |
| 11 | #define SDMMC_CDN_SRS02 0x8 |
| 12 | #define SDMMC_CDN_SRS03 0xC |
| 13 | #define SDMMC_CDN_SRS04 0x10 |
| 14 | #define SDMMC_CDN_SRS05 0x14 |
| 15 | #define SDMMC_CDN_SRS06 0x18 |
| 16 | #define SDMMC_CDN_SRS07 0x1C |
| 17 | #define SDMMC_CDN_SRS09 0x24 |
| 18 | #define SDMMC_CDN_SRS10 0x28 |
| 19 | #define SDMMC_CDN_SRS11 0x2C |
| 20 | #define SDMMC_CDN_SRS12 0x30 |
| 21 | #define SDMMC_CDN_SRS13 0x34 |
| 22 | #define SDMMC_CDN_SRS14 0x38 |
| 23 | |
| 24 | /* SRS03 */ |
| 25 | /* Response Type Select |
| 26 | * Defines the expected response length. |
| 27 | */ |
| 28 | #define SDMMC_CDN_RTS 16 |
| 29 | |
| 30 | /* Command CRC Check Enable |
| 31 | * When set to 1, the host checks if the CRC field of the response is valid. |
| 32 | * When 0, the CRC check is disabled and the CRC field of the response is ignored. |
| 33 | */ |
| 34 | #define SDMMC_CDN_CRCCE 19 |
| 35 | |
| 36 | /* Command Index |
| 37 | * This field contains a command number (index) of the command to be sent. |
| 38 | */ |
| 39 | #define SDMMC_CDN_CIDX 24 |
| 40 | |
| 41 | /* SRS09 */ |
| 42 | /* Card Inserted |
| 43 | * Indicates if the card is inserted inside the slot. |
| 44 | */ |
| 45 | #define SDMMC_CDN_CI 16 |
| 46 | |
| 47 | /* SRS10 */ |
| 48 | /* Data Transfer Width |
| 49 | * Bit used to configure DAT bus width to 1 or 4. |
| 50 | */ |
| 51 | #define SDMMC_CDN_DTW 1 |
| 52 | |
| 53 | /* Extended Data Transfer Width |
| 54 | * This bit is to enable/disable 8-bit DAT bus width mode. |
| 55 | */ |
| 56 | #define SDMMC_CDN_EDTW 5 |
| 57 | |
| 58 | /* SD Bus Power for VDD1 |
| 59 | * When set to 1, the VDD1 voltage is supplied to card/device. |
| 60 | */ |
| 61 | #define SDMMC_CDN_BP 8 |
| 62 | |
| 63 | /* SD Bus Voltage Select |
| 64 | * This field is used to configure VDD1 voltage level. |
| 65 | */ |
| 66 | #define SDMMC_CDN_BVS 9 |
| 67 | |
| 68 | /* SRS11 */ |
| 69 | /* Internal Clock Enable |
| 70 | * This field is designated to controls (enable/disable) external clock generator. |
| 71 | */ |
| 72 | #define SDMMC_CDN_ICE 0 |
| 73 | |
| 74 | /* Internal Clock Stable |
| 75 | * When 1, indicates that the clock on sdmclk pin of the host is stable. |
| 76 | * When 0, indicates that the clock is not stable . |
| 77 | */ |
| 78 | #define SDMMC_CDN_ICS 1 |
| 79 | |
| 80 | /* SD Clock Enable |
| 81 | * When set, SDCLK clock is enabled. |
| 82 | * When clear, SDCLK clock is stopped. |
| 83 | */ |
| 84 | #define SDMMC_CDN_SDCE 2 |
| 85 | |
| 86 | /* USDCLK Frequency Select |
| 87 | * This is used to calculate frequency of USDCLK clock. |
| 88 | */ |
| 89 | #define SDMMC_CDN_USDCLKFS 6 |
| 90 | |
| 91 | /* SDCLK Frequency Select |
| 92 | * This is used to calculate frequency of SDCLK clock. |
| 93 | */ |
| 94 | #define SDMMC_CDN_SDCLKFS 8 |
| 95 | |
| 96 | /* Data Timeout Counter Value |
| 97 | * This value determines the interval by which DAT line timeouts are detected |
| 98 | */ |
| 99 | #define SDMMC_CDN_DTCV 16 |
| 100 | |
| 101 | /* SRS12 */ |
| 102 | /* Command Complete |
| 103 | * Generated when the end bit of the response is received. |
| 104 | */ |
| 105 | #define SDMMC_CDN_CC 0 |
| 106 | |
| 107 | /* Transfer Complete |
| 108 | * Generated when the transfer which uses the DAT line is complete. |
| 109 | */ |
| 110 | #define SDMMC_CDN_TC 1 |
| 111 | |
| 112 | /* Error Interrupt |
| 113 | * The software can check for an error by reading this single bit first. |
| 114 | */ |
| 115 | #define SDMMC_CDN_EINT 15 |
| 116 | |
| 117 | /* SRS14 */ |
| 118 | /* Command Complete Interrupt Enable */ |
| 119 | #define SDMMC_CDN_CC_IE 0 |
| 120 | |
| 121 | /* Transfer Complete Interrupt Enable */ |
| 122 | #define SDMMC_CDN_TC_IE 1 |
| 123 | |
| 124 | /* DMA Interrupt Enable */ |
| 125 | #define SDMMC_CDN_DMAINT_IE 3 |
| 126 | |
| 127 | /* Combo PHY DLL registers */ |
| 128 | #define CP_DLL_REG_BASE (0x10B92000) |
| 129 | #define CP_DLL_DQ_TIMING_REG (0x00) |
| 130 | #define CP_DLL_DQS_TIMING_REG (0x04) |
| 131 | #define CP_DLL_GATE_LPBK_CTRL_REG (0x08) |
| 132 | #define CP_DLL_MASTER_CTRL_REG (0x0C) |
| 133 | #define CP_DLL_SLAVE_CTRL_REG (0x10) |
| 134 | #define CP_DLL_IE_TIMING_REG (0x14) |
| 135 | |
| 136 | #define CP_DQ_TIMING_REG_SDR (0x00000002) |
| 137 | #define CP_DQS_TIMING_REG_SDR (0x00100004) |
| 138 | #define CP_GATE_LPBK_CTRL_REG_SDR (0x00D80000) |
| 139 | #define CP_DLL_MASTER_CTRL_REG_SDR (0x00800000) |
| 140 | #define CP_DLL_SLAVE_CTRL_REG_SDR (0x00000000) |
| 141 | |
| 142 | #define CP_DLL(_reg) (CP_DLL_REG_BASE \ |
| 143 | + (CP_DLL_##_reg)) |
| 144 | |
| 145 | /* Control Timing Block registers */ |
| 146 | #define CP_CTB_REG_BASE (0x10B92080) |
| 147 | #define CP_CTB_CTRL_REG (0x00) |
| 148 | #define CP_CTB_TSEL_REG (0x04) |
| 149 | #define CP_CTB_GPIO_CTRL0 (0x08) |
| 150 | #define CP_CTB_GPIO_CTRL1 (0x0C) |
| 151 | #define CP_CTB_GPIO_STATUS0 (0x10) |
| 152 | #define CP_CTB_GPIO_STATUS1 (0x14) |
| 153 | |
| 154 | #define CP_CTRL_REG_SDR (0x00004040) |
| 155 | #define CP_TSEL_REG_SDR (0x00000000) |
| 156 | |
| 157 | #define CP_CTB(_reg) (CP_CTB_REG_BASE \ |
| 158 | + (CP_CTB_##_reg)) |
| 159 | |
| 160 | /* Combo PHY */ |
| 161 | #define SDMMC_CDN_REG_BASE 0x10808200 |
| 162 | #define PHY_DQ_TIMING_REG 0x2000 |
| 163 | #define PHY_DQS_TIMING_REG 0x2004 |
| 164 | #define PHY_GATE_LPBK_CTRL_REG 0x2008 |
| 165 | #define PHY_DLL_MASTER_CTRL_REG 0x200C |
| 166 | #define PHY_DLL_SLAVE_CTRL_REG 0x2010 |
| 167 | #define PHY_CTRL_REG 0x2080 |
| 168 | #define PHY_REG_ADDR_MASK 0xFFFF |
| 169 | #define PHY_REG_DATA_MASK 0xFFFFFFFF |
| 170 | |
| 171 | /* PHY_DQS_TIMING_REG */ |
| 172 | #define CP_USE_EXT_LPBK_DQS(x) ((x) << 22) //0x1 |
| 173 | #define CP_USE_LPBK_DQS(x) ((x) << 21) //0x1 |
| 174 | #define CP_USE_PHONY_DQS(x) ((x) << 20) //0x1 |
| 175 | #define CP_USE_PHONY_DQS_CMD(x) ((x) << 19) //0x1 |
| 176 | |
| 177 | /* PHY_GATE_LPBK_CTRL_REG */ |
| 178 | #define CP_SYNC_METHOD(x) ((x) << 31) //0x1 |
| 179 | #define CP_SW_HALF_CYCLE_SHIFT(x) ((x) << 28) //0x1 |
| 180 | #define CP_RD_DEL_SEL(x) ((x) << 19) //0x3f |
| 181 | #define CP_UNDERRUN_SUPPRESS(x) ((x) << 18) //0x1 |
| 182 | #define CP_GATE_CFG_ALWAYS_ON(x) ((x) << 6) //0x1 |
| 183 | |
| 184 | /* PHY_DLL_MASTER_CTRL_REG */ |
| 185 | #define CP_DLL_BYPASS_MODE(x) ((x) << 23) //0x1 |
| 186 | #define CP_DLL_START_POINT(x) ((x) << 0) //0xff |
| 187 | |
| 188 | /* PHY_DLL_SLAVE_CTRL_REG */ |
| 189 | #define CP_READ_DQS_CMD_DELAY(x) ((x) << 24) //0xff |
| 190 | #define CP_CLK_WRDQS_DELAY(x) ((x) << 16) //0xff |
| 191 | #define CP_CLK_WR_DELAY(x) ((x) << 8) //0xff |
| 192 | #define CP_READ_DQS_DELAY(x) ((x) << 0) //0xff |
| 193 | |
| 194 | /* PHY_DQ_TIMING_REG */ |
| 195 | #define CP_IO_MASK_ALWAYS_ON(x) ((x) << 31) //0x1 |
| 196 | #define CP_IO_MASK_END(x) ((x) << 27) //0x7 |
| 197 | #define CP_IO_MASK_START(x) ((x) << 24) //0x7 |
| 198 | #define CP_DATA_SELECT_OE_END(x) ((x) << 0) //0x7 |
| 199 | |
| 200 | /* PHY_CTRL_REG */ |
| 201 | #define CP_PHONY_DQS_TIMING_MASK 0x3F |
| 202 | #define CP_PHONY_DQS_TIMING_SHIFT 4 |
| 203 | |
| 204 | /* Shared Macros */ |
| 205 | #define SDMMC_CDN(_reg) (SDMMC_CDN_REG_BASE + \ |
| 206 | (SDMMC_CDN_##_reg)) |
| 207 | |
| 208 | struct cdns_sdmmc_combo_phy { |
| 209 | uint32_t cp_clk_wr_delay; |
| 210 | uint32_t cp_clk_wrdqs_delay; |
| 211 | uint32_t cp_data_select_oe_end; |
| 212 | uint32_t cp_dll_bypass_mode; |
| 213 | uint32_t cp_dll_locked_mode; |
| 214 | uint32_t cp_dll_start_point; |
| 215 | uint32_t cp_gate_cfg_always_on; |
| 216 | uint32_t cp_io_mask_always_on; |
| 217 | uint32_t cp_io_mask_end; |
| 218 | uint32_t cp_io_mask_start; |
| 219 | uint32_t cp_rd_del_sel; |
| 220 | uint32_t cp_read_dqs_cmd_delay; |
| 221 | uint32_t cp_read_dqs_delay; |
| 222 | uint32_t cp_sw_half_cycle_shift; |
| 223 | uint32_t cp_sync_method; |
| 224 | uint32_t cp_underrun_suppress; |
| 225 | uint32_t cp_use_ext_lpbk_dqs; |
| 226 | uint32_t cp_use_lpbk_dqs; |
| 227 | uint32_t cp_use_phony_dqs; |
| 228 | uint32_t cp_use_phony_dqs_cmd; |
| 229 | }; |
| 230 | |
| 231 | /* Function Prototype */ |
| 232 | |
| 233 | int cdns_sdmmc_write_phy_reg(uint32_t phy_reg_addr, uint32_t phy_reg_addr_value, |
| 234 | uint32_t phy_reg_data, uint32_t phy_reg_data_value); |
| 235 | int cdns_sd_card_detect(void); |
| 236 | int cdns_emmc_card_reset(void); |
| 237 | |
| 238 | #endif |