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Sandrine Bailleux798140d2014-07-17 16:06:39 +01001#
Summer Qin13b95c22018-03-02 15:51:14 +08002# Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
Sandrine Bailleux798140d2014-07-17 16:06:39 +01003#
dp-armfa3cf0b2017-05-03 09:38:09 +01004# SPDX-License-Identifier: BSD-3-Clause
Sandrine Bailleux798140d2014-07-17 16:06:39 +01005#
6
Achin Gupta1fa7eb62015-11-03 14:18:34 +00007JUNO_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
8 drivers/arm/gic/v2/gicv2_main.c \
9 drivers/arm/gic/v2/gicv2_helpers.c \
10 plat/common/plat_gicv2.c \
11 plat/arm/common/arm_gicv2.c
12
Vikram Kanigirifbb13012016-02-15 11:54:14 +000013JUNO_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c \
14 plat/arm/common/arm_cci.c
15
Soby Mathew9c708b52016-02-26 14:23:19 +000016JUNO_SECURITY_SOURCES := drivers/arm/tzc/tzc400.c \
Vikram Kanigiri70752bb2016-02-10 14:50:53 +000017 plat/arm/board/juno/juno_security.c \
dp-arm8f59e152017-02-27 12:21:43 +000018 plat/arm/board/juno/juno_trng.c \
Vikram Kanigiri70752bb2016-02-10 14:50:53 +000019 plat/arm/common/arm_tzc400.c
20
dp-armb3263b32017-02-28 14:43:15 +000021ifneq (${ENABLE_STACK_PROTECTOR}, 0)
22JUNO_SECURITY_SOURCES += plat/arm/board/juno/juno_stack_protector.c
23endif
Vikram Kanigirifbb13012016-02-15 11:54:14 +000024
Sathees Balya22576072018-09-03 17:41:13 +010025# Select SCMI/SDS drivers instead of SCPI/BOM driver for communicating with the
26# SCP during power management operations and for SCP RAM Firmware transfer.
27CSS_USE_SCMI_SDS_DRIVER := 1
28
29PLAT_INCLUDES := -Iplat/arm/board/juno/include \
30 -Iplat/arm/css/drivers/sds
Juan Castillo921b8772014-09-05 17:29:38 +010031
Yatharth Kocharede39cb2016-11-14 12:01:04 +000032PLAT_BL_COMMON_SOURCES := plat/arm/board/juno/${ARCH}/juno_helpers.S
Juan Castillo921b8772014-09-05 17:29:38 +010033
Yatharth Kocharede39cb2016-11-14 12:01:04 +000034# Flag to enable support for AArch32 state on JUNO
35JUNO_AARCH32_EL3_RUNTIME := 0
36$(eval $(call assert_boolean,JUNO_AARCH32_EL3_RUNTIME))
37$(eval $(call add_define,JUNO_AARCH32_EL3_RUNTIME))
38
Summer Qin13b95c22018-03-02 15:51:14 +080039# Flag to enable support for TZMP1 on JUNO
40JUNO_TZMP1 := 0
41$(eval $(call assert_boolean,JUNO_TZMP1))
42ifeq (${JUNO_TZMP1}, 1)
43$(eval $(call add_define,JUNO_TZMP1))
44endif
45
Soby Mathewbf169232017-11-14 14:10:10 +000046ifeq (${JUNO_AARCH32_EL3_RUNTIME}, 1)
47# Include BL32 in FIP
48NEED_BL32 := yes
49# BL31 is not required
50override BL31_SOURCES =
51
52# The BL32 needs to be built separately invoking the AARCH32 compiler and
53# be specifed via `BL32` build option.
54 ifneq (${ARCH}, aarch32)
55 override BL32_SOURCES =
56 endif
57endif
58
Yatharth Kocharede39cb2016-11-14 12:01:04 +000059ifeq (${ARCH},aarch64)
Dan Handley7bef8002015-03-19 19:22:44 +000060BL1_SOURCES += lib/cpus/aarch64/cortex_a53.S \
Brendan Jackmana443d222015-10-30 16:25:12 +000061 lib/cpus/aarch64/cortex_a57.S \
Juan Castillob6132f12015-10-06 14:01:35 +010062 lib/cpus/aarch64/cortex_a72.S \
Sathees Balya22576072018-09-03 17:41:13 +010063 plat/arm/board/juno/juno_err.c \
Yatharth Kochar736a3bf2015-10-11 14:14:55 +010064 plat/arm/board/juno/juno_bl1_setup.c \
dp-armb3263b32017-02-28 14:43:15 +000065 ${JUNO_INTERCONNECT_SOURCES} \
66 ${JUNO_SECURITY_SOURCES}
Juan Castillo921b8772014-09-05 17:29:38 +010067
Roberto Vargasb96ee4b2018-08-06 13:35:31 +010068BL2_SOURCES += lib/utils/mem_region.c \
Sathees Balya22576072018-09-03 17:41:13 +010069 plat/arm/board/juno/juno_err.c \
Roberto Vargasb96ee4b2018-08-06 13:35:31 +010070 plat/arm/board/juno/juno_bl2_setup.c \
71 plat/arm/common/arm_nor_psci_mem_protect.c \
Vikram Kanigiri70752bb2016-02-10 14:50:53 +000072 ${JUNO_SECURITY_SOURCES}
Juan Castillo921b8772014-09-05 17:29:38 +010073
Vikram Kanigiri70752bb2016-02-10 14:50:53 +000074BL2U_SOURCES += ${JUNO_SECURITY_SOURCES}
Yatharth Kochar3a11eda2015-10-14 15:28:11 +010075
Dan Handley7bef8002015-03-19 19:22:44 +000076BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \
Soby Mathew61e8d0b2015-10-12 17:32:29 +010077 lib/cpus/aarch64/cortex_a57.S \
Brendan Jackmana443d222015-10-30 16:25:12 +000078 lib/cpus/aarch64/cortex_a72.S \
Roberto Vargasb96ee4b2018-08-06 13:35:31 +010079 lib/utils/mem_region.c \
Soby Mathew47e43f22016-02-01 14:04:34 +000080 plat/arm/board/juno/juno_topology.c \
Roberto Vargasb96ee4b2018-08-06 13:35:31 +010081 plat/arm/board/common/drivers/norflash/norflash.c \
82 plat/arm/common/arm_nor_psci_mem_protect.c \
Vikram Kanigiri70752bb2016-02-10 14:50:53 +000083 ${JUNO_GIC_SOURCES} \
Vikram Kanigirifbb13012016-02-15 11:54:14 +000084 ${JUNO_INTERCONNECT_SOURCES} \
Vikram Kanigiri70752bb2016-02-10 14:50:53 +000085 ${JUNO_SECURITY_SOURCES}
Sathees Balya22576072018-09-03 17:41:13 +010086
87ifeq (${CSS_USE_SCMI_SDS_DRIVER},1)
88BL1_SOURCES += plat/arm/css/drivers/sds/sds.c
Yatharth Kocharede39cb2016-11-14 12:01:04 +000089endif
Juan Castillo921b8772014-09-05 17:29:38 +010090
Sathees Balya22576072018-09-03 17:41:13 +010091endif
92
Eleanor Bonnici8392aab2017-08-04 15:03:51 +010093# Errata workarounds for Cortex-A53:
94ERRATA_A53_826319 := 1
Douglas Raillardd56fb042017-06-19 15:38:02 +010095ERRATA_A53_835769 := 1
Eleanor Bonnici8392aab2017-08-04 15:03:51 +010096ERRATA_A53_836870 := 1
Douglas Raillardd56fb042017-06-19 15:38:02 +010097ERRATA_A53_843419 := 1
Andre Przywara00eefd92016-10-06 16:54:53 +010098ERRATA_A53_855873 := 1
Eleanor Bonnici8392aab2017-08-04 15:03:51 +010099
100# Errata workarounds for Cortex-A57:
Vikram Kanigirieade34c2016-01-20 15:57:35 +0000101ERRATA_A57_806969 := 0
Antonio Nino Diaz3f13c352017-02-24 11:39:22 +0000102ERRATA_A57_813419 := 1
Vikram Kanigirieade34c2016-01-20 15:57:35 +0000103ERRATA_A57_813420 := 1
Douglas Raillard71d4fe22017-02-28 17:56:15 +0000104ERRATA_A57_826974 := 1
105ERRATA_A57_826977 := 1
106ERRATA_A57_828024 := 1
107ERRATA_A57_829520 := 1
108ERRATA_A57_833471 := 1
Eleanor Bonnici8392aab2017-08-04 15:03:51 +0100109ERRATA_A57_859972 := 0
Douglas Raillard71d4fe22017-02-28 17:56:15 +0000110
Eleanor Bonnici8392aab2017-08-04 15:03:51 +0100111# Errata workarounds for Cortex-A72:
112ERRATA_A72_859971 := 0
Soby Mathew937488b2014-09-22 14:13:34 +0100113
114# Enable option to skip L1 data cache flush during the Cortex-A57 cluster
115# power down sequence
116SKIP_A57_L1_FLUSH_PWR_DWN := 1
Dan Handley7bef8002015-03-19 19:22:44 +0000117
David Cunadoc5b0c0f2017-10-31 23:19:21 +0000118# Do not enable SVE
119ENABLE_SVE_FOR_NS := 0
120
Dan Handley7bef8002015-03-19 19:22:44 +0000121include plat/arm/board/common/board_css.mk
122include plat/arm/common/arm_common.mk
123include plat/arm/soc/common/soc_css.mk
124include plat/arm/css/common/css_common.mk
Juan Castilloa08a5e72015-05-19 11:54:12 +0100125