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git01.mediatek.com / filogic / atf / a7c1ea742e2226afe643944e1647b15df1e8f2cc / . / plat / nvidia / tegra / include / t210 / tegra_def.h
blob: d24377da343e870605aef2bf082732a3e0d371f3 [file] [log] [blame]
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]1/*
Varun Wadekar0dc91812015-12-30 15:06:41 -0800[diff] [blame]2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#ifndef __TEGRA_DEF_H__
32#define __TEGRA_DEF_H__
33
34#include <platform_def.h>
35
36/*******************************************************************************
Varun Wadekar81b13832015-07-03 16:31:28 +0530[diff] [blame]37 * Power down state IDs
38 ******************************************************************************/
39#define PSTATE_ID_CORE_POWERDN 7
40#define PSTATE_ID_CLUSTER_IDLE 16
41#define PSTATE_ID_CLUSTER_POWERDN 17
42#define PSTATE_ID_SOC_POWERDN 27
43
44/*******************************************************************************
45 * This value is used by the PSCI implementation during the `SYSTEM_SUSPEND`
46 * call as the `state-id` field in the 'power state' parameter.
47 ******************************************************************************/
48#define PLAT_SYS_SUSPEND_STATE_ID PSTATE_ID_SOC_POWERDN
49
50/*******************************************************************************
Varun Wadekar3ce54992016-01-19 13:55:19 -0800[diff] [blame]51 * Platform power states (used by PSCI framework)
52 *
53 * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID
54 * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID
55 ******************************************************************************/
56#define PLAT_MAX_RET_STATE 1
57#define PLAT_MAX_OFF_STATE (PSTATE_ID_SOC_POWERDN + 1)
58
59/*******************************************************************************
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]60 * GIC memory map
61 ******************************************************************************/
62#define TEGRA_GICD_BASE 0x50041000
63#define TEGRA_GICC_BASE 0x50042000
64
65/*******************************************************************************
Varun Wadekarbc787442015-07-27 13:00:50 +0530[diff] [blame]66 * Tegra Memory Select Switch Controller constants
67 ******************************************************************************/
68#define TEGRA_MSELECT_BASE 0x50060000
69
70#define MSELECT_CONFIG 0x0
71#define ENABLE_WRAP_INCR_MASTER2_BIT (1 << 29)
72#define ENABLE_WRAP_INCR_MASTER1_BIT (1 << 28)
73#define ENABLE_WRAP_INCR_MASTER0_BIT (1 << 27)
74#define UNSUPPORTED_TX_ERR_MASTER2_BIT (1 << 25)
75#define UNSUPPORTED_TX_ERR_MASTER1_BIT (1 << 24)
76#define ENABLE_UNSUP_TX_ERRORS (UNSUPPORTED_TX_ERR_MASTER2_BIT | \
77 UNSUPPORTED_TX_ERR_MASTER1_BIT)
78#define ENABLE_WRAP_TO_INCR_BURSTS (ENABLE_WRAP_INCR_MASTER2_BIT | \
79 ENABLE_WRAP_INCR_MASTER1_BIT | \
80 ENABLE_WRAP_INCR_MASTER0_BIT)
81
82/*******************************************************************************
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]83 * Tegra micro-seconds timer constants
84 ******************************************************************************/
85#define TEGRA_TMRUS_BASE 0x60005010
86
87/*******************************************************************************
88 * Tegra Clock and Reset Controller constants
89 ******************************************************************************/
90#define TEGRA_CAR_RESET_BASE 0x60006000
91
92/*******************************************************************************
93 * Tegra Flow Controller constants
94 ******************************************************************************/
95#define TEGRA_FLOWCTRL_BASE 0x60007000
96
97/*******************************************************************************
98 * Tegra Secure Boot Controller constants
99 ******************************************************************************/
100#define TEGRA_SB_BASE 0x6000C200
101
102/*******************************************************************************
103 * Tegra Exception Vectors constants
104 ******************************************************************************/
105#define TEGRA_EVP_BASE 0x6000F000
106
107/*******************************************************************************
Varun Wadekar28dcc212016-07-20 10:28:51 -0700[diff] [blame]108 * Tegra Miscellaneous register constants
109 ******************************************************************************/
110#define TEGRA_MISC_BASE 0x70000000
111#define HARDWARE_REVISION_OFFSET 0x804
112
113/*******************************************************************************
Varun Wadekard2014c62015-10-29 10:37:28 +0530[diff] [blame]114 * Tegra UART controller base addresses
115 ******************************************************************************/
116#define TEGRA_UARTA_BASE 0x70006000
117#define TEGRA_UARTB_BASE 0x70006040
118#define TEGRA_UARTC_BASE 0x70006200
119#define TEGRA_UARTD_BASE 0x70006300
120#define TEGRA_UARTE_BASE 0x70006400
121
122/*******************************************************************************
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]123 * Tegra Power Mgmt Controller constants
124 ******************************************************************************/
125#define TEGRA_PMC_BASE 0x7000E400
126
127/*******************************************************************************
128 * Tegra Memory Controller constants
129 ******************************************************************************/
130#define TEGRA_MC_BASE 0x70019000
131
Varun Wadekar0dc91812015-12-30 15:06:41 -0800[diff] [blame]132/*******************************************************************************
133 * Tegra TZRAM constants
134 ******************************************************************************/
135#define TEGRA_TZRAM_BASE 0x7C010000
136#define TEGRA_TZRAM_SIZE 0x10000
137
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]138#endif /* __TEGRA_DEF_H__ */