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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Dan Handleye83b0ca2014-01-14 18:17:09 +00002 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31/dts-v1/;
32
33/memreserve/ 0x80000000 0x00010000;
34
35/ {
36};
37
38/ {
39 model = "FVP Base";
40 compatible = "arm,vfp-base", "arm,vexpress";
41 interrupt-parent = <&gic>;
42 #address-cells = <2>;
43 #size-cells = <2>;
44
45 chosen { };
46
47 aliases {
48 serial0 = &v2m_serial0;
49 serial1 = &v2m_serial1;
50 serial2 = &v2m_serial2;
51 serial3 = &v2m_serial3;
52 };
53
54 psci {
Soby Mathew1df077b2015-01-15 11:49:58 +000055 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
Achin Gupta4f6ad662013-10-25 09:08:21 +010056 method = "smc";
57 cpu_suspend = <0xc4000001>;
58 cpu_off = <0x84000002>;
59 cpu_on = <0xc4000003>;
60 };
61
62 cpus {
63 #address-cells = <2>;
64 #size-cells = <0>;
65
Achin Gupta5ab4fe42014-08-20 17:33:09 +010066 cpu-map {
67 cluster0 {
68 core0 {
69 cpu = <&CPU0>;
70 };
71 core1 {
72 cpu = <&CPU1>;
73 };
74 core2 {
75 cpu = <&CPU2>;
76 };
77 core3 {
78 cpu = <&CPU3>;
79 };
80 };
81
82 cluster1 {
83 core0 {
84 cpu = <&CPU4>;
85 };
86 core1 {
87 cpu = <&CPU5>;
88 };
89 core2 {
90 cpu = <&CPU6>;
91 };
92 core3 {
93 cpu = <&CPU7>;
94 };
95 };
96 };
97
98 idle-states {
99 entry-method = "arm,psci";
100
101 CPU_SLEEP_0: cpu-sleep-0 {
102 compatible = "arm,idle-state";
Juan Castillo3414f542015-04-16 14:17:49 +0100103 local-timer-stop;
104 arm,psci-suspend-param = <0x0010000>;
Achin Gupta5ab4fe42014-08-20 17:33:09 +0100105 entry-latency-us = <40>;
106 exit-latency-us = <100>;
107 min-residency-us = <150>;
108 };
109
110 CLUSTER_SLEEP_0: cluster-sleep-0 {
111 compatible = "arm,idle-state";
Juan Castillo3414f542015-04-16 14:17:49 +0100112 local-timer-stop;
113 arm,psci-suspend-param = <0x1010000>;
Achin Gupta5ab4fe42014-08-20 17:33:09 +0100114 entry-latency-us = <500>;
115 exit-latency-us = <1000>;
116 min-residency-us = <2500>;
117 };
118 };
119
120 CPU0:cpu@0 {
Achin Gupta4f6ad662013-10-25 09:08:21 +0100121 device_type = "cpu";
122 compatible = "arm,armv8";
123 reg = <0x0 0x0>;
124 enable-method = "psci";
Achin Gupta5ab4fe42014-08-20 17:33:09 +0100125 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100126 };
Achin Gupta5ab4fe42014-08-20 17:33:09 +0100127
128 CPU1:cpu@1 {
Achin Gupta4f6ad662013-10-25 09:08:21 +0100129 device_type = "cpu";
130 compatible = "arm,armv8";
131 reg = <0x0 0x1>;
132 enable-method = "psci";
Achin Gupta5ab4fe42014-08-20 17:33:09 +0100133 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100134 };
Achin Gupta5ab4fe42014-08-20 17:33:09 +0100135
136 CPU2:cpu@2 {
Achin Gupta4f6ad662013-10-25 09:08:21 +0100137 device_type = "cpu";
138 compatible = "arm,armv8";
139 reg = <0x0 0x2>;
140 enable-method = "psci";
Achin Gupta5ab4fe42014-08-20 17:33:09 +0100141 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100142 };
Achin Gupta5ab4fe42014-08-20 17:33:09 +0100143
144 CPU3:cpu@3 {
Achin Gupta4f6ad662013-10-25 09:08:21 +0100145 device_type = "cpu";
146 compatible = "arm,armv8";
147 reg = <0x0 0x3>;
148 enable-method = "psci";
Achin Gupta5ab4fe42014-08-20 17:33:09 +0100149 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100150 };
Achin Gupta5ab4fe42014-08-20 17:33:09 +0100151
152 CPU4:cpu@100 {
Achin Gupta4f6ad662013-10-25 09:08:21 +0100153 device_type = "cpu";
154 compatible = "arm,armv8";
155 reg = <0x0 0x100>;
156 enable-method = "psci";
Achin Gupta5ab4fe42014-08-20 17:33:09 +0100157 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100158 };
Achin Gupta5ab4fe42014-08-20 17:33:09 +0100159
160 CPU5:cpu@101 {
Achin Gupta4f6ad662013-10-25 09:08:21 +0100161 device_type = "cpu";
162 compatible = "arm,armv8";
163 reg = <0x0 0x101>;
164 enable-method = "psci";
Achin Gupta5ab4fe42014-08-20 17:33:09 +0100165 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100166 };
Achin Gupta5ab4fe42014-08-20 17:33:09 +0100167
168 CPU6:cpu@102 {
Achin Gupta4f6ad662013-10-25 09:08:21 +0100169 device_type = "cpu";
170 compatible = "arm,armv8";
171 reg = <0x0 0x102>;
172 enable-method = "psci";
Achin Gupta5ab4fe42014-08-20 17:33:09 +0100173 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100174 };
Achin Gupta5ab4fe42014-08-20 17:33:09 +0100175
176 CPU7:cpu@103 {
Achin Gupta4f6ad662013-10-25 09:08:21 +0100177 device_type = "cpu";
178 compatible = "arm,armv8";
179 reg = <0x0 0x103>;
180 enable-method = "psci";
Achin Gupta5ab4fe42014-08-20 17:33:09 +0100181 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100182 };
183 };
184
185 memory@80000000 {
186 device_type = "memory";
Juan Castillo7055ca42014-05-16 15:33:15 +0100187 reg = <0x00000000 0x80000000 0 0x7F000000>,
Achin Gupta4f6ad662013-10-25 09:08:21 +0100188 <0x00000008 0x80000000 0 0x80000000>;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100189 };
190
Harry Liebel34988592013-11-11 13:24:47 +0000191 gic: interrupt-controller@2f000000 {
Achin Gupta4f6ad662013-10-25 09:08:21 +0100192 compatible = "arm,gic-v3";
193 #interrupt-cells = <3>;
Harry Liebel34988592013-11-11 13:24:47 +0000194 #address-cells = <2>;
195 #size-cells = <2>;
196 ranges;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100197 interrupt-controller;
198 reg = <0x0 0x2f000000 0 0x10000>, // GICD
199 <0x0 0x2f100000 0 0x200000>, // GICR
200 <0x0 0x2c000000 0 0x2000>, // GICC
201 <0x0 0x2c010000 0 0x2000>, // GICH
Harry Liebel34988592013-11-11 13:24:47 +0000202 <0x0 0x2c02f000 0 0x2000>; // GICV
Achin Gupta4f6ad662013-10-25 09:08:21 +0100203 interrupts = <1 9 4>;
Harry Liebel34988592013-11-11 13:24:47 +0000204
205 its: its@2f020000 {
206 compatible = "arm,gic-v3-its";
207 msi-controller;
208 reg = <0x0 0x2f020000 0x0 0x20000>; // GITS
209 };
Achin Gupta4f6ad662013-10-25 09:08:21 +0100210 };
211
212 timer {
213 compatible = "arm,armv8-timer";
214 interrupts = <1 13 0xff01>,
215 <1 14 0xff01>,
216 <1 11 0xff01>,
217 <1 10 0xff01>;
218 clock-frequency = <100000000>;
219 };
220
221 timer@2a810000 {
222 compatible = "arm,armv7-timer-mem";
223 reg = <0x0 0x2a810000 0x0 0x10000>;
224 clock-frequency = <100000000>;
225 #address-cells = <2>;
226 #size-cells = <2>;
227 ranges;
Harry Liebelcef93392014-04-01 19:27:38 +0100228 frame@2a830000 {
229 frame-number = <1>;
230 interrupts = <0 26 4>;
231 reg = <0x0 0x2a830000 0x0 0x10000>;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100232 };
233 };
234
235 pmu {
236 compatible = "arm,armv8-pmuv3";
237 interrupts = <0 60 4>,
238 <0 61 4>,
239 <0 62 4>,
240 <0 63 4>;
241 };
242
243 smb {
244 compatible = "simple-bus";
245
246 #address-cells = <2>;
247 #size-cells = <1>;
248 ranges = <0 0 0 0x08000000 0x04000000>,
249 <1 0 0 0x14000000 0x04000000>,
250 <2 0 0 0x18000000 0x04000000>,
251 <3 0 0 0x1c000000 0x04000000>,
252 <4 0 0 0x0c000000 0x04000000>,
253 <5 0 0 0x10000000 0x04000000>;
254
255 #interrupt-cells = <1>;
256 interrupt-map-mask = <0 0 63>;
Harry Liebel34988592013-11-11 13:24:47 +0000257 interrupt-map = <0 0 0 &gic 0 0 0 0 4>,
258 <0 0 1 &gic 0 0 0 1 4>,
259 <0 0 2 &gic 0 0 0 2 4>,
260 <0 0 3 &gic 0 0 0 3 4>,
261 <0 0 4 &gic 0 0 0 4 4>,
262 <0 0 5 &gic 0 0 0 5 4>,
263 <0 0 6 &gic 0 0 0 6 4>,
264 <0 0 7 &gic 0 0 0 7 4>,
265 <0 0 8 &gic 0 0 0 8 4>,
266 <0 0 9 &gic 0 0 0 9 4>,
267 <0 0 10 &gic 0 0 0 10 4>,
268 <0 0 11 &gic 0 0 0 11 4>,
269 <0 0 12 &gic 0 0 0 12 4>,
270 <0 0 13 &gic 0 0 0 13 4>,
271 <0 0 14 &gic 0 0 0 14 4>,
272 <0 0 15 &gic 0 0 0 15 4>,
273 <0 0 16 &gic 0 0 0 16 4>,
274 <0 0 17 &gic 0 0 0 17 4>,
275 <0 0 18 &gic 0 0 0 18 4>,
276 <0 0 19 &gic 0 0 0 19 4>,
277 <0 0 20 &gic 0 0 0 20 4>,
278 <0 0 21 &gic 0 0 0 21 4>,
279 <0 0 22 &gic 0 0 0 22 4>,
280 <0 0 23 &gic 0 0 0 23 4>,
281 <0 0 24 &gic 0 0 0 24 4>,
282 <0 0 25 &gic 0 0 0 25 4>,
283 <0 0 26 &gic 0 0 0 26 4>,
284 <0 0 27 &gic 0 0 0 27 4>,
285 <0 0 28 &gic 0 0 0 28 4>,
286 <0 0 29 &gic 0 0 0 29 4>,
287 <0 0 30 &gic 0 0 0 30 4>,
288 <0 0 31 &gic 0 0 0 31 4>,
289 <0 0 32 &gic 0 0 0 32 4>,
290 <0 0 33 &gic 0 0 0 33 4>,
291 <0 0 34 &gic 0 0 0 34 4>,
292 <0 0 35 &gic 0 0 0 35 4>,
293 <0 0 36 &gic 0 0 0 36 4>,
294 <0 0 37 &gic 0 0 0 37 4>,
295 <0 0 38 &gic 0 0 0 38 4>,
296 <0 0 39 &gic 0 0 0 39 4>,
297 <0 0 40 &gic 0 0 0 40 4>,
298 <0 0 41 &gic 0 0 0 41 4>,
299 <0 0 42 &gic 0 0 0 42 4>;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100300
Juan Castillo4dc4a472014-08-12 11:17:06 +0100301 /include/ "rtsm_ve-motherboard-no_psci.dtsi"
Achin Gupta4f6ad662013-10-25 09:08:21 +0100302 };
303
304 panels {
305 panel@0 {
306 compatible = "panel";
307 mode = "XVGA";
308 refresh = <60>;
309 xres = <1024>;
310 yres = <768>;
311 pixclock = <15748>;
312 left_margin = <152>;
313 right_margin = <48>;
314 upper_margin = <23>;
315 lower_margin = <3>;
316 hsync_len = <104>;
317 vsync_len = <4>;
318 sync = <0>;
319 vmode = "FB_VMODE_NONINTERLACED";
320 tim2 = "TIM2_BCD", "TIM2_IPC";
321 cntl = "CNTL_LCDTFT", "CNTL_BGR", "CNTL_LCDVCOMP(1)";
322 caps = "CLCD_CAP_5551", "CLCD_CAP_565", "CLCD_CAP_888";
323 bpp = <16>;
324 };
325 };
326};