Alexei Fedorov | 2f13d6c | 2020-02-21 10:17:26 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2015-2020, Arm Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <arch_helpers.h> |
| 9 | #include <common/debug.h> |
| 10 | #include <common/interrupt_props.h> |
| 11 | #include <drivers/arm/gicv3.h> |
| 12 | #include "gicv3_private.h" |
| 13 | |
| 14 | /******************************************************************************* |
| 15 | * GIC Redistributor functions |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 16 | * Note: The raw register values correspond to multiple interrupt `id`s and |
| 17 | * the number of interrupt `id`s involved depends on the register accessed. |
Alexei Fedorov | 2f13d6c | 2020-02-21 10:17:26 +0000 | [diff] [blame] | 18 | ******************************************************************************/ |
| 19 | |
| 20 | /* |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 21 | * Accessor to set the byte corresponding to interrupt `id` |
| 22 | * in GIC Redistributor IPRIORITYR and IPRIORITYRE. |
Alexei Fedorov | 2f13d6c | 2020-02-21 10:17:26 +0000 | [diff] [blame] | 23 | */ |
| 24 | void gicr_set_ipriorityr(uintptr_t base, unsigned int id, unsigned int pri) |
| 25 | { |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 26 | GICR_WRITE_8(IPRIORITY, base, id, (uint8_t)(pri & GIC_PRI_MASK)); |
Alexei Fedorov | 2f13d6c | 2020-02-21 10:17:26 +0000 | [diff] [blame] | 27 | } |
| 28 | |
| 29 | /* |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 30 | * Accessors to get/set/clear the bit corresponding to interrupt `id` |
| 31 | * from GIC Redistributor IGROUPR0 and IGROUPRE |
Alexei Fedorov | 2f13d6c | 2020-02-21 10:17:26 +0000 | [diff] [blame] | 32 | */ |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 33 | unsigned int gicr_get_igroupr(uintptr_t base, unsigned int id) |
Alexei Fedorov | 2f13d6c | 2020-02-21 10:17:26 +0000 | [diff] [blame] | 34 | { |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 35 | return GICR_GET_BIT(IGROUP, base, id); |
Alexei Fedorov | 2f13d6c | 2020-02-21 10:17:26 +0000 | [diff] [blame] | 36 | } |
| 37 | |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 38 | void gicr_set_igroupr(uintptr_t base, unsigned int id) |
Alexei Fedorov | 2f13d6c | 2020-02-21 10:17:26 +0000 | [diff] [blame] | 39 | { |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 40 | GICR_SET_BIT(IGROUP, base, id); |
Alexei Fedorov | 2f13d6c | 2020-02-21 10:17:26 +0000 | [diff] [blame] | 41 | } |
| 42 | |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 43 | void gicr_clr_igroupr(uintptr_t base, unsigned int id) |
Alexei Fedorov | 2f13d6c | 2020-02-21 10:17:26 +0000 | [diff] [blame] | 44 | { |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 45 | GICR_CLR_BIT(IGROUP, base, id); |
Alexei Fedorov | 2f13d6c | 2020-02-21 10:17:26 +0000 | [diff] [blame] | 46 | } |
| 47 | |
| 48 | /* |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 49 | * Accessors to get/set/clear the bit corresponding to interrupt `id` |
| 50 | * from GIC Redistributor IGRPMODR0 and IGRPMODRE |
Alexei Fedorov | 2f13d6c | 2020-02-21 10:17:26 +0000 | [diff] [blame] | 51 | */ |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 52 | unsigned int gicr_get_igrpmodr(uintptr_t base, unsigned int id) |
Alexei Fedorov | 2f13d6c | 2020-02-21 10:17:26 +0000 | [diff] [blame] | 53 | { |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 54 | return GICR_GET_BIT(IGRPMOD, base, id); |
Alexei Fedorov | 2f13d6c | 2020-02-21 10:17:26 +0000 | [diff] [blame] | 55 | } |
| 56 | |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 57 | void gicr_set_igrpmodr(uintptr_t base, unsigned int id) |
Alexei Fedorov | 2f13d6c | 2020-02-21 10:17:26 +0000 | [diff] [blame] | 58 | { |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 59 | GICR_SET_BIT(IGRPMOD, base, id); |
Alexei Fedorov | 2f13d6c | 2020-02-21 10:17:26 +0000 | [diff] [blame] | 60 | } |
| 61 | |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 62 | void gicr_clr_igrpmodr(uintptr_t base, unsigned int id) |
Alexei Fedorov | 2f13d6c | 2020-02-21 10:17:26 +0000 | [diff] [blame] | 63 | { |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 64 | GICR_CLR_BIT(IGRPMOD, base, id); |
Alexei Fedorov | 2f13d6c | 2020-02-21 10:17:26 +0000 | [diff] [blame] | 65 | } |
| 66 | |
| 67 | /* |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 68 | * Accessor to write the bit corresponding to interrupt `id` |
| 69 | * in GIC Redistributor ISENABLER0 and ISENABLERE |
Alexei Fedorov | 2f13d6c | 2020-02-21 10:17:26 +0000 | [diff] [blame] | 70 | */ |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 71 | void gicr_set_isenabler(uintptr_t base, unsigned int id) |
Alexei Fedorov | 2f13d6c | 2020-02-21 10:17:26 +0000 | [diff] [blame] | 72 | { |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 73 | GICR_WRITE_BIT(ISENABLE, base, id); |
Alexei Fedorov | 2f13d6c | 2020-02-21 10:17:26 +0000 | [diff] [blame] | 74 | } |
| 75 | |
| 76 | /* |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 77 | * Accessor to write the bit corresponding to interrupt `id` |
| 78 | * in GIC Redistributor ICENABLER0 and ICENABLERE |
Alexei Fedorov | 2f13d6c | 2020-02-21 10:17:26 +0000 | [diff] [blame] | 79 | */ |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 80 | void gicr_set_icenabler(uintptr_t base, unsigned int id) |
Alexei Fedorov | 2f13d6c | 2020-02-21 10:17:26 +0000 | [diff] [blame] | 81 | { |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 82 | GICR_WRITE_BIT(ICENABLE, base, id); |
Alexei Fedorov | 2f13d6c | 2020-02-21 10:17:26 +0000 | [diff] [blame] | 83 | } |
| 84 | |
| 85 | /* |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 86 | * Accessor to get the bit corresponding to interrupt `id` |
| 87 | * in GIC Redistributor ISACTIVER0 and ISACTIVERE |
Alexei Fedorov | 2f13d6c | 2020-02-21 10:17:26 +0000 | [diff] [blame] | 88 | */ |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 89 | unsigned int gicr_get_isactiver(uintptr_t base, unsigned int id) |
Alexei Fedorov | 2f13d6c | 2020-02-21 10:17:26 +0000 | [diff] [blame] | 90 | { |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 91 | return GICR_GET_BIT(ISACTIVE, base, id); |
Alexei Fedorov | 2f13d6c | 2020-02-21 10:17:26 +0000 | [diff] [blame] | 92 | } |
| 93 | |
| 94 | /* |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 95 | * Accessor to clear the bit corresponding to interrupt `id` |
| 96 | * in GIC Redistributor ICPENDR0 and ICPENDRE |
Alexei Fedorov | 2f13d6c | 2020-02-21 10:17:26 +0000 | [diff] [blame] | 97 | */ |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 98 | void gicr_set_icpendr(uintptr_t base, unsigned int id) |
Alexei Fedorov | 2f13d6c | 2020-02-21 10:17:26 +0000 | [diff] [blame] | 99 | { |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 100 | GICR_WRITE_BIT(ICPEND, base, id); |
Alexei Fedorov | 2f13d6c | 2020-02-21 10:17:26 +0000 | [diff] [blame] | 101 | } |
| 102 | |
| 103 | /* |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 104 | * Accessor to write the bit corresponding to interrupt `id` |
| 105 | * in GIC Redistributor ISPENDR0 and ISPENDRE |
Alexei Fedorov | 2f13d6c | 2020-02-21 10:17:26 +0000 | [diff] [blame] | 106 | */ |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 107 | void gicr_set_ispendr(uintptr_t base, unsigned int id) |
Alexei Fedorov | 2f13d6c | 2020-02-21 10:17:26 +0000 | [diff] [blame] | 108 | { |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 109 | GICR_WRITE_BIT(ISPEND, base, id); |
Alexei Fedorov | 2f13d6c | 2020-02-21 10:17:26 +0000 | [diff] [blame] | 110 | } |
| 111 | |
| 112 | /* |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 113 | * Accessor to set the bit fields corresponding to interrupt `id` |
| 114 | * in GIC Redistributor ICFGR0, ICFGR1 and ICFGRE |
Alexei Fedorov | 2f13d6c | 2020-02-21 10:17:26 +0000 | [diff] [blame] | 115 | */ |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 116 | void gicr_set_icfgr(uintptr_t base, unsigned int id, unsigned int cfg) |
Alexei Fedorov | 2f13d6c | 2020-02-21 10:17:26 +0000 | [diff] [blame] | 117 | { |
| 118 | /* Interrupt configuration is a 2-bit field */ |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 119 | unsigned int bit_shift = BIT_NUM(ICFG, id) << 1U; |
Alexei Fedorov | 2f13d6c | 2020-02-21 10:17:26 +0000 | [diff] [blame] | 120 | |
| 121 | /* Clear the field, and insert required configuration */ |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 122 | mmio_clrsetbits_32(base + GICR_OFFSET(ICFG, id), |
| 123 | (uint32_t)GIC_CFG_MASK << bit_shift, |
| 124 | (cfg & GIC_CFG_MASK) << bit_shift); |
Alexei Fedorov | 2f13d6c | 2020-02-21 10:17:26 +0000 | [diff] [blame] | 125 | } |