| Pankaj Gupta | 74f7b14 | 2020-12-09 14:02:38 +0530 | [diff] [blame] | 1 | /* |
| Pankaj Gupta | 7834b46 | 2021-03-25 15:15:52 +0530 | [diff] [blame] | 2 | * Copyright 2020-2021 NXP |
| Pankaj Gupta | 74f7b14 | 2020-12-09 14:02:38 +0530 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | * |
| 6 | */ |
| 7 | |
| 8 | #ifndef SCFG_H |
| 9 | #define SCFG_H |
| 10 | |
| 11 | #ifdef CONFIG_CHASSIS_2 |
| 12 | |
| 13 | /* SCFG register offsets */ |
| 14 | #define SCFG_CORE0_SFT_RST_OFFSET 0x0130 |
| 15 | #define SCFG_SNPCNFGCR_OFFSET 0x01A4 |
| 16 | #define SCFG_CORESRENCR_OFFSET 0x0204 |
| 17 | #define SCFG_RVBAR0_0_OFFSET 0x0220 |
| 18 | #define SCFG_RVBAR0_1_OFFSET 0x0224 |
| 19 | #define SCFG_COREBCR_OFFSET 0x0680 |
| 20 | #define SCFG_RETREQCR_OFFSET 0x0424 |
| 21 | |
| 22 | #define SCFG_COREPMCR_OFFSET 0x042C |
| 23 | #define COREPMCR_WFIL2 0x1 |
| 24 | |
| 25 | #define SCFG_GIC400_ADDR_ALIGN_OFFSET 0x0188 |
| 26 | #define SCFG_BOOTLOCPTRH_OFFSET 0x0600 |
| 27 | #define SCFG_BOOTLOCPTRL_OFFSET 0x0604 |
| 28 | #define SCFG_SCRATCHRW2_OFFSET 0x0608 |
| 29 | #define SCFG_SCRATCHRW3_OFFSET 0x060C |
| 30 | |
| 31 | /* SCFG bit fields */ |
| 32 | #define SCFG_SNPCNFGCR_SECRDSNP 0x80000000 |
| Jiafei Pan | e85dbdb | 2021-10-21 16:01:47 +0800 | [diff] [blame] | 33 | #define SCFG_SNPCNFGCR_SECWRSNP 0x40000000 |
| 34 | |
| 35 | /* GIC Address Align Register */ |
| 36 | #define SCFG_GIC400_ADDR_ALIGN_4KMODE_MASK 0x80000000 |
| 37 | #define SCFG_GIC400_ADDR_ALIGN_4KMODE_EN 0x80000000 |
| 38 | #define SCFG_GIC400_ADDR_ALIGN_4KMODE_DIS 0x0 |
| 39 | |
| Pankaj Gupta | 74f7b14 | 2020-12-09 14:02:38 +0530 | [diff] [blame] | 40 | #endif /* CONFIG_CHASSIS_2 */ |
| 41 | |
| 42 | #ifndef __ASSEMBLER__ |
| 43 | #include <endian.h> |
| 44 | #include <lib/mmio.h> |
| 45 | |
| 46 | #ifdef NXP_SCFG_BE |
| 47 | #define scfg_in32(a) bswap32(mmio_read_32((uintptr_t)(a))) |
| 48 | #define scfg_out32(a, v) mmio_write_32((uintptr_t)(a), bswap32(v)) |
| 49 | #define scfg_setbits32(a, v) mmio_setbits_32((uintptr_t)(a), v) |
| 50 | #define scfg_clrbits32(a, v) mmio_clrbits_32((uintptr_t)(a), v) |
| 51 | #define scfg_clrsetbits32(a, clear, set) \ |
| 52 | mmio_clrsetbits_32((uintptr_t)(a), clear, set) |
| Jiafei Pan | d59bd1a | 2021-09-26 15:51:15 +0800 | [diff] [blame] | 53 | #elif defined(NXP_SCFG_LE) |
| Pankaj Gupta | 74f7b14 | 2020-12-09 14:02:38 +0530 | [diff] [blame] | 54 | #define scfg_in32(a) mmio_read_32((uintptr_t)(a)) |
| 55 | #define scfg_out32(a, v) mmio_write_32((uintptr_t)(a), v) |
| 56 | #define scfg_setbits32(a, v) mmio_setbits_32((uintptr_t)(a), v) |
| 57 | #define scfg_clrbits32(a, v) mmio_clrbits_32((uintptr_t)(a), v) |
| 58 | #define scfg_clrsetbits32(a, clear, set) \ |
| 59 | mmio_clrsetbits_32((uintptr_t)(a), clear, set) |
| 60 | #else |
| 61 | #error Please define CCSR SCFG register endianness |
| 62 | #endif |
| 63 | #endif /* __ASSEMBLER__ */ |
| 64 | |
| 65 | #endif /* SCFG_H */ |