blob: 81df9a61a9c162426d7e5459768f86513216d0ba [file] [log] [blame]
Pankaj Gupta74f7b142020-12-09 14:02:38 +05301/*
2 * Copyright 2020 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 *
6 */
7
8#ifndef SCFG_H
9#define SCFG_H
10
11#ifdef CONFIG_CHASSIS_2
12
13/* SCFG register offsets */
14#define SCFG_CORE0_SFT_RST_OFFSET 0x0130
15#define SCFG_SNPCNFGCR_OFFSET 0x01A4
16#define SCFG_CORESRENCR_OFFSET 0x0204
17#define SCFG_RVBAR0_0_OFFSET 0x0220
18#define SCFG_RVBAR0_1_OFFSET 0x0224
19#define SCFG_COREBCR_OFFSET 0x0680
20#define SCFG_RETREQCR_OFFSET 0x0424
21
22#define SCFG_COREPMCR_OFFSET 0x042C
23#define COREPMCR_WFIL2 0x1
24
25#define SCFG_GIC400_ADDR_ALIGN_OFFSET 0x0188
26#define SCFG_BOOTLOCPTRH_OFFSET 0x0600
27#define SCFG_BOOTLOCPTRL_OFFSET 0x0604
28#define SCFG_SCRATCHRW2_OFFSET 0x0608
29#define SCFG_SCRATCHRW3_OFFSET 0x060C
30
31/* SCFG bit fields */
32#define SCFG_SNPCNFGCR_SECRDSNP 0x80000000
33#define SCFG_SNPCNFGCR_SECWRSNP 0x40000000
34#endif /* CONFIG_CHASSIS_2 */
35
36#ifndef __ASSEMBLER__
37#include <endian.h>
38#include <lib/mmio.h>
39
40#ifdef NXP_SCFG_BE
41#define scfg_in32(a) bswap32(mmio_read_32((uintptr_t)(a)))
42#define scfg_out32(a, v) mmio_write_32((uintptr_t)(a), bswap32(v))
43#define scfg_setbits32(a, v) mmio_setbits_32((uintptr_t)(a), v)
44#define scfg_clrbits32(a, v) mmio_clrbits_32((uintptr_t)(a), v)
45#define scfg_clrsetbits32(a, clear, set) \
46 mmio_clrsetbits_32((uintptr_t)(a), clear, set)
47#elif defined(NXP_GUR_LE)
48#define scfg_in32(a) mmio_read_32((uintptr_t)(a))
49#define scfg_out32(a, v) mmio_write_32((uintptr_t)(a), v)
50#define scfg_setbits32(a, v) mmio_setbits_32((uintptr_t)(a), v)
51#define scfg_clrbits32(a, v) mmio_clrbits_32((uintptr_t)(a), v)
52#define scfg_clrsetbits32(a, clear, set) \
53 mmio_clrsetbits_32((uintptr_t)(a), clear, set)
54#else
55#error Please define CCSR SCFG register endianness
56#endif
57#endif /* __ASSEMBLER__ */
58
59#endif /* SCFG_H */