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Varun Wadekar3c959932016-03-03 13:09:08 -08001/*
Pritesh Raithatha9eb5db52017-01-02 19:42:31 +05302 * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
Pritesh Raithatha75c94432018-08-03 15:48:15 +05303 * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
Varun Wadekar3c959932016-03-03 13:09:08 -08004 *
dp-armfa3cf0b2017-05-03 09:38:09 +01005 * SPDX-License-Identifier: BSD-3-Clause
Varun Wadekar3c959932016-03-03 13:09:08 -08006 */
7
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +00008#ifndef SMMU_H
9#define SMMU_H
Varun Wadekar3c959932016-03-03 13:09:08 -080010
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011#include <lib/mmio.h>
12
Pritesh Raithatha9eb5db52017-01-02 19:42:31 +053013#include <memctrl_v2.h>
Varun Wadekar3c959932016-03-03 13:09:08 -080014#include <tegra_def.h>
15
Anthony Zhou59fd6152017-03-13 15:34:08 +080016#define SMMU_CBn_ACTLR (0x4U)
Varun Wadekar3c959932016-03-03 13:09:08 -080017
18/*******************************************************************************
19 * SMMU Global Secure Aux. Configuration Register
20 ******************************************************************************/
Anthony Zhou59fd6152017-03-13 15:34:08 +080021#define SMMU_GSR0_SECURE_ACR 0x10U
22#define SMMU_GNSR_ACR (SMMU_GSR0_SECURE_ACR + 0x400U)
23#define SMMU_GSR0_PGSIZE_SHIFT 16U
24#define SMMU_GSR0_PGSIZE_4K (0U << SMMU_GSR0_PGSIZE_SHIFT)
25#define SMMU_GSR0_PGSIZE_64K (1U << SMMU_GSR0_PGSIZE_SHIFT)
Varun Wadekara32a8b62018-12-10 13:20:49 -080026#define SMMU_ACR_CACHE_LOCK_ENABLE_BIT (1ULL << 26U)
27#define SMMU_GSR0_PER (0x20200U)
Varun Wadekarea709c32016-04-20 17:14:15 -070028
29/*******************************************************************************
30 * SMMU Global Aux. Control Register
31 ******************************************************************************/
Anthony Zhou0e07e452017-07-26 17:16:54 +080032#define SMMU_CBn_ACTLR_CPRE_BIT (1ULL << 1U)
Varun Wadekar3c959932016-03-03 13:09:08 -080033
Varun Wadekara32a8b62018-12-10 13:20:49 -080034/* SMMU IDs currently supported by the driver */
35enum {
36 TEGRA_SMMU0 = 0U,
37 TEGRA_SMMU1 = 1U,
38 TEGRA_SMMU2 = 2U
39};
40
41static inline uint32_t tegra_smmu_read_32(uint32_t smmu_id, uint32_t off)
42{
43 uint32_t ret = 0U;
44
45#if defined(TEGRA_SMMU0_BASE)
46 if (smmu_id == TEGRA_SMMU0) {
47 ret = mmio_read_32(TEGRA_SMMU0_BASE + (uint64_t)off);
48 }
49#endif
50
51#if defined(TEGRA_SMMU1_BASE)
52 if (smmu_id == TEGRA_SMMU1) {
53 ret = mmio_read_32(TEGRA_SMMU1_BASE + (uint64_t)off);
54 }
55#endif
56
57#if defined(TEGRA_SMMU2_BASE)
58 if (smmu_id == TEGRA_SMMU2) {
59 ret = mmio_read_32(TEGRA_SMMU2_BASE + (uint64_t)off);
60 }
61#endif
62
63 return ret;
64}
65
66static inline void tegra_smmu_write_32(uint32_t smmu_id,
67 uint32_t off, uint32_t val)
68{
69#if defined(TEGRA_SMMU0_BASE)
70 if (smmu_id == TEGRA_SMMU0) {
71 mmio_write_32(TEGRA_SMMU0_BASE + (uint64_t)off, val);
72 }
73#endif
74
75#if defined(TEGRA_SMMU1_BASE)
76 if (smmu_id == TEGRA_SMMU1) {
77 mmio_write_32(TEGRA_SMMU1_BASE + (uint64_t)off, val);
78 }
79#endif
80
81#if defined(TEGRA_SMMU2_BASE)
82 if (smmu_id == TEGRA_SMMU2) {
83 mmio_write_32(TEGRA_SMMU2_BASE + (uint64_t)off, val);
84 }
85#endif
86}
87
Varun Wadekar3c959932016-03-03 13:09:08 -080088void tegra_smmu_init(void);
Steven Kao7fd30f52017-07-25 11:29:46 +080089uint32_t plat_get_num_smmu_devices(void);
Varun Wadekar3c959932016-03-03 13:09:08 -080090
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +000091#endif /* SMMU_H */