| Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 1 | /* |
| Pritesh Raithatha | 9eb5db5 | 2017-01-02 19:42:31 +0530 | [diff] [blame] | 2 | * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. |
| Pritesh Raithatha | 75c9443 | 2018-08-03 15:48:15 +0530 | [diff] [blame^] | 3 | * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. |
| Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 4 | * |
| dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 5 | * SPDX-License-Identifier: BSD-3-Clause |
| Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 6 | */ |
| 7 | |
| Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 8 | #ifndef SMMU_H |
| 9 | #define SMMU_H |
| Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 10 | |
| Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 11 | #include <lib/mmio.h> |
| 12 | |
| Pritesh Raithatha | 9eb5db5 | 2017-01-02 19:42:31 +0530 | [diff] [blame] | 13 | #include <memctrl_v2.h> |
| Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 14 | #include <tegra_def.h> |
| 15 | |
| Anthony Zhou | 59fd615 | 2017-03-13 15:34:08 +0800 | [diff] [blame] | 16 | #define SMMU_CBn_ACTLR (0x4U) |
| Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 17 | |
| 18 | /******************************************************************************* |
| 19 | * SMMU Global Secure Aux. Configuration Register |
| 20 | ******************************************************************************/ |
| Anthony Zhou | 59fd615 | 2017-03-13 15:34:08 +0800 | [diff] [blame] | 21 | #define SMMU_GSR0_SECURE_ACR 0x10U |
| 22 | #define SMMU_GNSR_ACR (SMMU_GSR0_SECURE_ACR + 0x400U) |
| 23 | #define SMMU_GSR0_PGSIZE_SHIFT 16U |
| 24 | #define SMMU_GSR0_PGSIZE_4K (0U << SMMU_GSR0_PGSIZE_SHIFT) |
| 25 | #define SMMU_GSR0_PGSIZE_64K (1U << SMMU_GSR0_PGSIZE_SHIFT) |
| 26 | #define SMMU_ACR_CACHE_LOCK_ENABLE_BIT (1U << 26) |
| Varun Wadekar | ea709c3 | 2016-04-20 17:14:15 -0700 | [diff] [blame] | 27 | |
| 28 | /******************************************************************************* |
| 29 | * SMMU Global Aux. Control Register |
| 30 | ******************************************************************************/ |
| Anthony Zhou | 0e07e45 | 2017-07-26 17:16:54 +0800 | [diff] [blame] | 31 | #define SMMU_CBn_ACTLR_CPRE_BIT (1ULL << 1U) |
| Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 32 | |
| Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 33 | void tegra_smmu_init(void); |
| Steven Kao | 7fd30f5 | 2017-07-25 11:29:46 +0800 | [diff] [blame] | 34 | uint32_t plat_get_num_smmu_devices(void); |
| Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 35 | |
| Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 36 | #endif /* SMMU_H */ |