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Varun Wadekar0f3baa02015-07-16 11:36:33 +05301/*
Varun Wadekare34bc3d2017-04-28 08:43:33 -07002 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
Varun Wadekar0f3baa02015-07-16 11:36:33 +05303 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Varun Wadekar0f3baa02015-07-16 11:36:33 +05305 */
6
Varun Wadekarb7b45752015-12-28 14:55:41 -08007#include <arch_helpers.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00008#include <common/bl_common.h>
9#include <lib/xlat_tables/xlat_tables_v2.h>
Varun Wadekare34bc3d2017-04-28 08:43:33 -070010#include <platform.h>
Varun Wadekar0f3baa02015-07-16 11:36:33 +053011#include <tegra_def.h>
Varun Wadekarb7b45752015-12-28 14:55:41 -080012#include <tegra_private.h>
Varun Wadekar0f3baa02015-07-16 11:36:33 +053013
Varun Wadekar0f3baa02015-07-16 11:36:33 +053014/* sets of MMIO ranges setup */
15#define MMIO_RANGE_0_ADDR 0x50000000
16#define MMIO_RANGE_1_ADDR 0x60000000
17#define MMIO_RANGE_2_ADDR 0x70000000
18#define MMIO_RANGE_SIZE 0x200000
19
20/*
21 * Table of regions to map using the MMU.
22 */
23static const mmap_region_t tegra_mmap[] = {
24 MAP_REGION_FLAT(MMIO_RANGE_0_ADDR, MMIO_RANGE_SIZE,
25 MT_DEVICE | MT_RW | MT_SECURE),
26 MAP_REGION_FLAT(MMIO_RANGE_1_ADDR, MMIO_RANGE_SIZE,
27 MT_DEVICE | MT_RW | MT_SECURE),
28 MAP_REGION_FLAT(MMIO_RANGE_2_ADDR, MMIO_RANGE_SIZE,
29 MT_DEVICE | MT_RW | MT_SECURE),
30 {0}
31};
32
33/*******************************************************************************
34 * Set up the pagetables as per the platform memory map & initialize the MMU
35 ******************************************************************************/
36const mmap_region_t *plat_get_mmio_map(void)
37{
38 /* MMIO space */
39 return tegra_mmap;
40}
41
Varun Wadekare34bc3d2017-04-28 08:43:33 -070042/*******************************************************************************
43 * The Tegra power domain tree has a single system level power domain i.e. a
44 * single root node. The first entry in the power domain descriptor specifies
45 * the number of power domains at the highest power level.
46 *******************************************************************************
47 */
48const unsigned char tegra_power_domain_tree_desc[] = {
49 /* No of root nodes */
50 1,
51 /* No of clusters */
52 PLATFORM_CLUSTER_COUNT,
53 /* No of CPU cores */
54 PLATFORM_CORE_COUNT,
55};
56
57/*******************************************************************************
58 * This function returns the Tegra default topology tree information.
59 ******************************************************************************/
60const unsigned char *plat_get_power_domain_tree_desc(void)
61{
62 return tegra_power_domain_tree_desc;
63}
64
Antonio Nino Diaze82e29c2016-05-19 10:00:28 +010065unsigned int plat_get_syscnt_freq2(void)
Varun Wadekar0f3baa02015-07-16 11:36:33 +053066{
67 return 12000000;
68}
Varun Wadekard2014c62015-10-29 10:37:28 +053069
70/*******************************************************************************
71 * Maximum supported UART controllers
72 ******************************************************************************/
73#define TEGRA132_MAX_UART_PORTS 5
74
75/*******************************************************************************
76 * This variable holds the UART port base addresses
77 ******************************************************************************/
78static uint32_t tegra132_uart_addresses[TEGRA132_MAX_UART_PORTS + 1] = {
79 0, /* undefined - treated as an error case */
80 TEGRA_UARTA_BASE,
81 TEGRA_UARTB_BASE,
82 TEGRA_UARTC_BASE,
83 TEGRA_UARTD_BASE,
84 TEGRA_UARTE_BASE,
85};
86
87/*******************************************************************************
88 * Retrieve the UART controller base to be used as the console
89 ******************************************************************************/
90uint32_t plat_get_console_from_id(int id)
91{
92 if (id > TEGRA132_MAX_UART_PORTS)
93 return 0;
94
95 return tegra132_uart_addresses[id];
96}
Varun Wadekarb7b45752015-12-28 14:55:41 -080097
98/*******************************************************************************
99 * Initialize the GIC and SGIs
100 ******************************************************************************/
101void plat_gic_setup(void)
102{
103 tegra_gic_setup(NULL, 0);
104}